Abstract: A digital video color camera having three solid-state image sensing devices and an analog-to-digital converter that converts the signal from the image sensing devices to a digital signal and a digital signal processing circuit that processes the output of the analog-to-digital converter further includes a clock generator that generates a first sampling clock signal used to drive the solid-state image sensing devices and a second clock signal having a frequency (f2) that is higher than the first frequency (f1) used to drive the digital signal processing circuit. An optical low-pass filter and an electrical low-pass filter are provided between the image sensing devices and the analog-to-digital converter in one embodiment, and in another embodiment the electrical low-pass filter is after the analog-to-digital converter. The optical low-pass filter has a frequency characteristic chosen to depress the frequency band component between the frequencies f1-1/2f2 and f1.

Abstract: In a solid state television camera for producing output signals corresponding to an object image detected by a solid state image sensor, positions of picture elements having crystal defects and the output signal levels of such defective components are previously stored as the defective picture element data in a memory device. Defect compensating signals corresponding to the actual image pickup operating states are formed on the basis of the defect picture element data read out from the memory device to correct the output signals of such defective picture elements in a manner to provide the image pickup output signals with superior picture quality.

Abstract: A CCD register, for example a horizontal output register of a CCD imager, includes an output precharge circuit with a capacitance. The voltage across the capacitance is supplied to an output terminal of the CCD register and has first, second and third durations repeatedly. The first duration is a precharge, the second duration is a reference duration, and the third duration is a signal. An output signal processing circuit provided for the CCD register includes a clamp circuit for clamping the output signal at the output terminal of the CCD register in such a manner that the voltage of the reference duration becomes a stable clamp voltage; a clip circuit for clipping the output signal of the clamp circuit in such that the voltage of the precharge duration is clipped to a clip level; and a low-pass filter supplied with the output of the clip circuit for generating a transferred signal.

Abstract: A clamp circuit for a solid-state imaging device which includes a clamp circuit for clamping at a black reference voltage level a video signal at a signal level which is obtained when an optical black portion formed on the solid-state imaging device is read, a detection circuit for detecting the increase in voltage of the optical black portion, a circuit for interrupting vertical transfer clock signals of the solid-state imaging device during at least one horizontal line interval during a vertical blanking period, and a switching circuit which when the detection means detects an abnormal voltage of the optical black portion, supplies a clamp pulse which is generated with a timing associated with the interruption of the transfer clock signals instead of the clamp pulse of the optical black portion.

Abstract: An apparatus and method for registration adjustment are disclosed, in which when effecting so-called registration adjustment for positioning solid-state image sensor element (31r, 31g and 31b) used for a solid-state image sensor apparatus at predetermined positions of an image sensor optical system (30), a registration adjustment test chart (10) having at least one horizontal or vertical shade recurrence pattern at a recurrence pitch (.tau.p) in a particular relation to the picture element pitch (.tau.c) of the solid-state image sensor elements (31r, 31g and 31b) is imaged, and the positional deviation in six directions of the solid-state image sensor elements (31r, 31g and 31b) is measured on the basis of the beat component of the image sensor output of the solid-state image sensor elements (31r, 31g and 31b) based on the difference between the picture element pitch (.tau.c) and the shade recurrence pitch (.tau.px).

Abstract: An optical filter for use in a solid state color camera containing a plurality of solid state image sensing devices having a predetermined horizontal scanning direction, the filter including a first crystal plate for separating an incident ray into an ordinary ray and extraordinary rays in a direction of 45.degree. with respect to the horizontal scanning direction of said solid state image sensing devices, a second crystal plate for separating the incident ray thereof into an ordinary ray and extraordinary rays in a direction which coincides with the horizontal scanning direction, and a third crystal plate for separating the incident ray into an ordinary ray and extraordinary ray in a direction of -45.degree. with respect to the horizontal scanning direction. The second crystal plate is located between the first and third crystal plates, and the three plates are bonded together in the form of a laminate.

Abstract: An image enhancer for a color television camera using plural CCD image sensors is proposed, wherein an image of an object on the image sensors for generating the green signal is displaced in the horizontal direction by half the alignment pitch of picture elements relative to the image of the object projected on the image sensors for generating red and blue signals. A vertical image enhancing signal is generated from the green signal only, and a horizontal image enhancing signal is generated from the equally added sum of the green signal and a signal formed of at least the red signal. A composite image enhancing signal is formed by adding the vertical and horizontal image enhancing signals, and is added to the primary color signals.

Abstract: A charge-coupled device (CCD) camera with a smear reducer circuit is disclosed, which includes a CCD for generating a pickup signal, a memory for storing an extracted smear signal from the pickup signal and, a level selector circuit for cutting off a noise contained in the smear signal with level less than a predetermined level in the smear signals from the memory. The output of this level selector circuit is subtracted from the pickup signal to thereby obtain a pickup signal with the smear reduced as well as a noise component suppressed.

Abstract: A digital encoder for use with digital luminance and chrominance signals having black levels includes a level adjusting circuit which adjusts the chrominance and luminance signals to establish a predetermined relationship between the black levels of the level-adjusted chrominance and luminance signals, a chrominance signal with a predetermined relatively large dynamic range thereof modulating circuit which generates a modulated chrominance signal from the level-adjusted chrominance signal, an adding circuit which receives the modulated chrominance signal and the level-adjusted luminance signal and provides an encoded color video signal therefrom, an attenuator circuit which attenuates the encoded color video signal and a circuit for combining sync and burst signals with the attenuated encoded color video signal and with a predetermined pedestal level to provide a composite color video signal within the predetermined dynamic range.

Abstract: A digital signal processing circuit, for example, a digital signal adder circuit suitable for use in a digital color encoder for generating a digital composite color video signal from three digital primary color signals. At least two input digital signals are respectively supplied to a signal delay circuit which generates the digital signal in the form of skew bits wherein the higher bit is given a larger delay. The output signals of the signal delay circuit are supplied to an adder circuit in which the small number of bits of the digital signals are added during one clock interval. And, the output signal of the adder circuit is supplied to a further delay circuit which generates a digital signal in the form of linear bits wherein any bit in originally the same clock interval is given the same delay.

Abstract: A color video signal processing apparatus which utilizes a digital luminance data and first and second color difference signals which are digitized at a first sampling frequency and formed by matrix operation wherein at least one of the first or second color difference data is sampled at a second sampling frequency which comprises the first sampling frequency divided by an integer with the band width of the sample output being limited to a predetermined band width with a digital filter and the luminance and first and second color difference signals which have had their band width limited comprising the color video signal which is to be transmitted.

Abstract: A solid state television camera having a solid state image sensing device, such as CCD image sensing device and an iris for controlling the amount of light from an image irradiated on the image sensing device. The iris is controlled by the peak level of a smear signal of a horizontal scanning line during a vertical blanking interval so that the smear signal contained in a video signal from the image sensing device is reduced. Further, the iris can be controlled by the average level of the smear signal instead of the average level of the video signal of one field as the smear signal has the whole information of the image of one field, that causes the construction of detecting circuit to be very simple and the fidelity of the iris control to be high.

Abstract: A digital color camera is disclosed, which includes a circuit for generating first, second and third digital color signals, each at a rate of 4f.sub.sc (where f.sub.sc represents a color subcarrier frequency) from the outputs of first, second and third imagers. A circuit forms a digital luminance signal from the first, second and third digital color signals, and a circuit forms a dot-sequential color difference signal with the first and second digital color difference signals appearing alternately every 1/4f.sub. sc from the first, second and third digital color difference signals and a circuit passes a dot-sequential digital color difference signal through a digital filter so as to limit the band widths of the first and second digital color difference signals and the overall circuit provides improved color TV signals which are formed with simpler circuit means.

Abstract: A digital color encoder for a television camera in which during digitally modulating a carrier of 3f.sub.sc (f.sub.sc is a color subcarrier frequency) with a digital color signal which is obtained by sampling input video information data at a sampling pulse rate having a frequency of 3(n/m)f.sub.sc (with m and n being relatively small integers) at N line the digital color signal is amplitude modulated by 3-phase modulation vectors each having a phase difference of 2/3.pi. from each other so as to produce a digitally modulated color signal. At N+1 line, the digital color signal is amplitude modulated by the 3-phase modulation vectors each having a phase opposite to that at the N line so as to produce an output of N+1 line which is then phase inverted to provide a digital modulated color signal. Thus, a digital color television signal with color phase having the standard television signal format is obtained.

Abstract: A solidstate digital television camera which has a solid state image sensing device, an A-D converter for converting the output of the image sensing device to a digital color signal, a filter for providing a predetermined filter characteristic to the digital color signal, and a digital color modulator for modulating the output of the above filter to produce a digital modulated signal.In the digital television camera, the processing rate between the solid state image sensing device and the filter is selected to have a sampling rate equal to that of the solid state image sensing device, or (n/m)pF.sub.sc where f.sub.sc is a color subcarrier frequency, p is 3 or 4, and m and n are relatively small integers. The processing rate for the remaining elements is selected to be pf.sub.sc. In addition, a D-D converter for converting the processing rate from (n/m)pF.sub.sc to pf.sub.sc is provided between the filter and the digital modulator.