Patents by Inventor Takashi Endo

Takashi Endo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7454017
    Abstract: An object of the present invention is to a provide tamper resistant information processing unit that is used as an IC card with a high level of security. To achieve the above-mentioned object, the information unit of the present invention comprises: a program container part for storing a program; a memory for storing data; an arithmetic unit for performing specified processing according to the program; a data bus for connecting the memory to the arithmetic unit; and a transform function for transforming a logical address and a physical address of the memory, said logical address being used for arithmetic operation by the arithmetic unit, said physical address being set at random corresponding to the logical address at each arithmetic operation or every time the information processing unit is started up.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: November 18, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Masahiro Kaminaga, Takashi Watanabe, Takashi Endo
  • Patent number: 7451485
    Abstract: A malfunction detection system is provided that can continue or terminate processing appropriately even if a malfunction occurs in an information processing unit. In this regard, the information processing unit receives branch direction information, carries out a conditional branch depending on the branch direction information, and performs an applicable operation on data I. At this time, the information processing unit performs an applicable operation on data J, other than the operated data I, in the conditional branch path and outputs the result for examination, thereby enabling validation of the conditional branch.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: November 11, 2008
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Takashi Watanabe, Takashi Endo, Masahiro Kaminaga, Kunihiko Nakada, Yuuichirou Nariyoshi, Chiaki Tanimoto
  • Publication number: 20080271001
    Abstract: In programming in high-level language, a method of generating a program supporting external specifications for generating secure codes having high tamper-resistance and automatically generating an executable program having tamper-resistance with regard to a portion designated by a user is provided. A syntax analysis step, an intermediate representation generation step, a register allocation step, an optimization processing step, an assembly language generation step, a machine language generation step and a machine language program linkage step are executed. And between finish of reading of the source program and generating the executable program, a tamper-resistant code insertion step of automatically generating a code having tamper-resistance coping with unjust analysis of an operation content of the executable program is executed to the source program, the intermediate representation, the assembly language program or the machine language program based on an instruction of a user.
    Type: Application
    Filed: September 11, 2007
    Publication date: October 30, 2008
    Inventors: Yo Nonomura, Shunsuke Ota, Takashi Endo, Takashi Tsukamoto, Ichiro Kyushima, Hiromi Nagayama, Kenichi Hirane, Yoshiyuki Amanuma
  • Publication number: 20080231766
    Abstract: A projector includes: an optical modulator including a liquid crystal cell, a first optical element formed of an optical material having positive uniaxiality, a second optical element formed of an optical material having positive uniaxiality, a third optical element that includes at least one optical film formed of an optical material having a refractive index anisotropy, and a pair of polarization elements; an adjustment mechanism that makes it possible to adjust an optical azimuth of a first group, which has at least one of the first optical element, the second optical element, and at least one optical film included in the third optical element, with respect to a fixed optical azimuth of a second group as a remainder excluding the element included in the first group among the first to third optical elements; a light source that generates light for illuminating the optical modulator; and a projection optical system that projects the light that has passed through the optical modulator.
    Type: Application
    Filed: March 17, 2008
    Publication date: September 25, 2008
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hiroaki Yanai, Takashi Endo
  • Publication number: 20080174705
    Abstract: A liquid crystal device includes a liquid crystal cell containing liquid crystal operating in twisted nematic mode, a first compensating element disposed either on the light entrance side or on the light exit side of the liquid crystal cell and made of an optical material having positive uniaxial characteristics, a second compensating element disposed either on the light entrance side or on the light exit side of the liquid crystal cell and made of an optical material having positive uniaxial characteristics, a third compensating element disposed at least either on the light entrance side or on the light exit side of the liquid crystal cell and made of an optical material which satisfies the following condition for parameters Re and Rth concerning refractive index anisotropy: ?Rth<Re<Rth, and a pair of polarizing elements between which the liquid crystal cell, the first compensating element, the second compensating element, and the third compensating element are disposed.
    Type: Application
    Filed: January 8, 2008
    Publication date: July 24, 2008
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Takashi ENDO, Hiroaki YANAI
  • Publication number: 20080117385
    Abstract: A liquid crystal device includes: a liquid crystal cell which includes liquid crystals operating in a vertical alignment mode, in which optic axes of the liquid crystals are inclined and oriented at a predetermined pre-tilt angle with respect to a normal line to an incident surface in an off-state; an optical compensator having an optic axis in a direction inclined with respect to the surface, that is, an orientation direction of the liquid crystals of the liquid crystal cell in an off-state.
    Type: Application
    Filed: March 12, 2007
    Publication date: May 22, 2008
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Takashi ENDO
  • Publication number: 20080055551
    Abstract: An optical element includes a first substrate, a second substrate, a retardation plate made of an inorganic material, having refractive index anisotropy, and having a thin plate like main part to be disposed between the first substrate and the second substrate, the main part being formed to be thin in comparison with a thickness of the first substrate and a thickness of the second substrate, a first adhesive layer for filling a gap between the first substrate and the retardation plate, and a second adhesive layer for filling a gap between the retardation plate and the second substrate.
    Type: Application
    Filed: August 23, 2007
    Publication date: March 6, 2008
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Takashi ENDO, Toshiaki HASHIZUME
  • Publication number: 20080049191
    Abstract: A projector that includes an optical device is provided. The optical device includes a first flat plate formed of a negative uniaxial refractive material, the first plate having an incidence plane and an emission plane parallel to each other and having an optical axis and a second flat plate formed of a positive uniaxial refractive material, the second flat plate having an incidence plane and an emission plane parallel to the incidence plane of the first flat plate; respectively, and having an optical axis substantially parallel to the optical axis of the first flat plate. In the optical device of the projector, a predetermined phase difference is given to light using the first and second flat plates as a pair by adjusting the thickness of the first flat plate and the thickness of the second flat plate.
    Type: Application
    Filed: August 10, 2007
    Publication date: February 28, 2008
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Takashi ENDO
  • Publication number: 20070255980
    Abstract: A program to be executed by a computer is divided into a plurality of code blocks, and, a unique code block ID is allotted to each code block. At the moment when the execution of the program is started, the code block ID corresponding to the execution start address is written in a memory, and in the case when the control transits from the code block to other code block, by use of code block operation values obtained beforehand from these two code block IDs thereof, the code block ID in the memory is updated, and it is judged whether the updated code block ID in the memory and the code block ID allotted to the code block as the execution objective are identical or not so that a control flow error is detected.
    Type: Application
    Filed: April 12, 2007
    Publication date: November 1, 2007
    Inventors: Takashi ENDO, Toshio Okochi, Takashi Watanabe, Shunsuke Ota, Tatsuya Kameyama
  • Patent number: 7284133
    Abstract: An information processing unit and methods therefore which render it more difficult to infer information being processed within an information processing unit by observing the unit's current consumption or electromagnetic radiation. Specifically, the information processing unit preferably encrypts and decrypts data when the data is read from/written to memories within the unit. The encryption/decryption process may include the use of multiple cryptographic keys, permutated data storage locations, randomly generated keys, and permutated data processing steps.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: October 16, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Watanabe, Masahiro Kaminaga, Takashi Endo, Seiichi Kumano
  • Publication number: 20070195949
    Abstract: An increase in safety from attacks by use of hardware-like methods by small-sized hardware is achieved. An encryption processing device includes a logical circuit capable of programmably setting logics for executing cipher processing, a memory that stores plural pieces of logical configuration information corresponding to an identical cipher processing algorithm, and a CPU that selectively sets plural logics corresponding to an identical cipher processing algorithm in the logical circuit. Even in processing using an identical cipher key, by changing the logic of the logical circuit for each processing, power consumption in cipher processing can be varied, and places a timing in which malfunctions occur can be varied. Moreover, an increase in the scale of hardware for realizing plural logics can be curbed.
    Type: Application
    Filed: January 17, 2007
    Publication date: August 23, 2007
    Inventors: Toshio Okochi, Takashi Endo, Takashi Watanabe, Tatsuya Kameyama, Shunsuke Ota
  • Patent number: 7254718
    Abstract: The subject of the disclosed technology is, when a crypto-processing is performed utilizing an information processing device buried in an IC card, etc., to decrease the relationship between the waveform of the consumption current and the contents of the crypto-processing as a countermeasure against a tamper which observes the waveform of a consumption current. A solution means is shown in the following. When a decryption processing of an RSA cryptogram is performed according to CRT, in step 608, for every unit bit block of XP a modular exponentiation calculation is performed, and the partial result of CP up to the calculated bit block is stored in a memory. In step 609, for every unit bit block of XQ a modular exponentiation calculation is performed and the partial result of CQ up to the calculated bit block is stored in a memory.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: August 7, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Kaminaga, Takashi Endo, Takashi Watanabe, Masaru Ohki
  • Patent number: 7201326
    Abstract: An object of the present invention is to prevent secret information that is being internally processed from being inferred through operational information of a secured device, including the current consumption information. One solution is provided by an information processing device having at least a key generation apparatus that generates key data automatically, an encryption unit that encrypts data with the corresponding key data, a register that stores a plurality of encrypted data items with the corresponding encryption key data items, and an arithmetic unit that performs operations using data expressed with the corresponding encryption key data and new key data as the input, encrypts the operation result with new input key data, and outputs the result, thereby being capable of performing internal processing on an encrypted data expression. Accordingly, only encrypted data is transferred on the internal or external data bus line.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: April 10, 2007
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Takashi Endo, Masahiro Kaminaga, Takashi Watanabe, Kunihiko Nakada, Takashi Tsukamoto
  • Patent number: 7086087
    Abstract: It is a technological object of the present invention to provide an information processing device, a card and a card system that have a high level of security. In order to achieve the object described above, the present invention provides a data processing apparatus comprising at least a first information processing device and a second information processing device connected to the first information processing device by a signal line, the data processing apparatus having a means for changing power consumption on the signal line during transmission of a signal through the signal line in accordance with an actual state of the power consumption that would be observed when the means were not used.
    Type: Grant
    Filed: June 22, 2000
    Date of Patent: August 1, 2006
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Masahiro Kaminaga, Takashi Endo, Masaru Ohki, Takashi Tsukamoto, Hiroshi Watase, Chiaki Terauchi, Kunihiko Nakada, Nobutaka Nagasaki, Satoshi Taira, Yuuichirou Nariyoshi, Yasuko Fukuzawa
  • Publication number: 20060094741
    Abstract: The present invention relates to a therapeutic agent for neuropathic pain containing, as an active ingredient, a compound represented by general formula (I) or a pharmacologically acceptable acid addition salt thereof: (wherein R1, R2, R3, R4, R5, R6, R7, R8, A, and B have the same definitions as those described in the specification), and an animal model produced by administering (+)-4a-(3-hydroxyphenyl)-2-methyl-1,2,3,4,4a,5,12,12a-octohydro-trans-quinolino[2,3-g]isoquinoline. The present invention makes it possible to perform drug treatment for neuropathic pain. The therapeutic effect of a compound against neuropathic pain can also be evaluated.
    Type: Application
    Filed: August 18, 2005
    Publication date: May 4, 2006
    Applicant: Toray Industries, Inc., a corporation of Japan
    Inventors: Hiroshi Nagase, Takashi Endo, Kuniaki Kawamura, Toshiaki Tanaka, Tomohiko Suzuki, Tsutomu Suzuki, Yasushi Kuraishi, Kimiyasu Shiraki
  • Patent number: 6986054
    Abstract: The present invention makes it difficult for unauthorized parties to estimate processing and a secret key based upon the waveforms of power consumption of an IC card chip by changing a processing order in the IC card chip so that it is not estimated by the attackers. In an information processing apparatus comprising storing means having a program storing part for storing programs and a data storing part for storing data, an operation processing unit, means for inputting data to be operated on in the operation processing unit, and means for outputting operation processing results on the data by the operation processing unit, an arithmetic operation method is provided which comprises the steps of: for two integers K1 and K2, when finding a value F(K, A) of a function F satisfying F(K1+K2, A)=F(K1, A)?F(K2, A) (? denotes an arithmetic operation in a communtative semigroup S. K designates an integer and A designates an element of S), decomposing the K to the sum of m integers K[0]+K[1]+ . . .
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: January 10, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Kaminaga, Takashi Endo, Takashi Watanabe
  • Patent number: 6968354
    Abstract: The disclosed technology of the present invention relates to an information processing device such as an IC card, and specifically to the overflow processing which occurs in a modular multiplication operation during crypto-processing. Such overflow processing exhibits a particular pattern of consumption current. It is the subject of the present invention to decrease the relationship between the data processing and the pattern of the consumption current. In the processing procedures for performing a modular exponentiation operation according to the 2 bit addition chain method, the modular multiplication operation to be executed is selected at random, the selected modular multiplication operation is executed for each 2 bits, the correction of the result is performed, and the result of the calculation (i.e, a corrected value or uncorrected value) is outputted.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: November 22, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Kaminaga, Takashi Endo, Takashi Watanabe, Masaru Ohki
  • Patent number: 6952139
    Abstract: An oscillator operated with an external power source or an external save power source is provided comprising: a clock signal generation unit for generating and outputting a clock signal; a power-on detection unit for detecting the power-on of the external power source; a power-off detection unit for detecting the power-off of the external power source; a running time count unit for counting the running time from a time of the power-on detection signal being input to a time of the power-off detection signal being input; storage means for storing accumulated running time up to a power-on time of the external power source; and a control unit for reading the running time at the time of the power-off detection signal being input, reading the accumulated running time from the storage means, adding the running time to the accumulated running time, and storing the addition result as a new accumulated running time in the storage means.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: October 4, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Takashi Endo, Yoichi Fujii
  • Publication number: 20050116780
    Abstract: An oscillator operated with an external power source or an external save power source is provided comprising: a clock signal generation unit for generating and outputting a clock signal; a power-on detection unit for detecting the power-on of the external power source; a power-off detection unit for detecting the power-off of the external power source; a running time count unit for counting the running time from a time of the power-on detection signal being input to a time of the power-off detection signal being input; storage means for storing accumulated running time up to a power-on time of the external power source; and a control unit for reading the running time at the time of the power-off detection signal being input, reading the accumulated running time from the storage means, adding the running time to the accumulated running time, and storing the addition result as a new accumulated running time in the storage means.
    Type: Application
    Filed: March 19, 2004
    Publication date: June 2, 2005
    Inventors: Takashi Endo, Yoichi Fujii
  • Patent number: D558813
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: January 1, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiro Muramatsu, Takashi Endo