Patents by Inventor Takashi Gotou

Takashi Gotou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuit wiring laying-out apparatus, method of laying-out a circuit, signal-bearing medium embodying a program of laying-out wiring, wiring layout, and method of using a wiring layout
    Publication number: 20060081881
    Abstract: A circuit wiring laying-out apparatus includes a wiring device that moves automatically a wiring in a first region to a second region, to make uniform a number of wirings in the circuit.
    Type: Application
    Filed: October 17, 2005
    Publication date: April 20, 2006
    Applicant: NEC Corporation
    Inventor: Takashi Gotou
  • Method for manufacturing semiconductor device
    Patent number: 6849550
    Abstract: A method for manufacturing a semiconductor device that forms a connection hole with high electric reliability even when the semiconductor device is designed to be highly integrated. The semiconductor device includes a lower layer wiring and an interlayer insulation film, which is formed on the lower layer wiring and has a connection hole connected with the lower layer wiring. The method includes forming the connection hole by etching the interlayer insulation film. The connection hole is formed by etching part of the lower layer wiring under a first etching condition through physical reaction in at least the vicinity of the lower layer wiring, and by etching part of the interlayer insulation film under a second etching condition that guarantees a selective ratio relative to the lower layer wiring.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: February 1, 2005
    Assignee: Sanyo Electric Co. Ltd.
    Inventors: Yoshinari Ichihashi, Norihiro Ikeda, Takashi Gotou, Ryousuke Usui, Tatsuya Fujishima
  • Method for manufacturing semiconductor device
    Publication number: 20030060053
    Abstract: A method for manufacturing a semiconductor device that forms a connection hole with high electric reliability even when the semiconductor device is designed to be highly integrated. The semiconductor device includes a lower layer wiring and an interlayer insulation film, which is formed on the lower layer wiring and has a connection hole connected with the lower layer wiring. The method includes forming the connection hole by etching the interlayer insulation film. The connection hole is formed by etching part of the lower layer wiring under a first etching condition through physical reaction in at least the vicinity of the lower layer wiring, and by etching part of the interlayer insulation film under a second etching condition that guarantees a selective ratio relative to the lower layer wiring.
    Type: Application
    Filed: July 9, 2002
    Publication date: March 27, 2003
    Inventors: Yoshinari Ichihashi, Norihiro Ikeda, Takashi Gotou, Ryousuke Usui, Tatsuya Fujishima
  • 2,6-dichloro-4-pyridinemethanol derivatives and agricultural chemicals
    Patent number: 6281231
    Abstract: The object is to provide a novel compound, with which there is little possibility of phytotoxicity for crop plants, and which is greatly effective in controlling various plant diseases caused by viruses pathogenic to plants, by bacteria, and by molds, and to provide agricultural chemicals, particularly agents for controlling plant diseases, containing this compound, 2,6-dichloro-4-pyridinemethanol, and/or a benzoic acid ester thereof as an active ingredient.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: August 28, 2001
    Assignee: Dainippon Ink and Chemical, Inc.
    Inventors: Toru Asada, Mika Iiyama, Hiroyuki Tsuboi, Takashi Gotou