Patents by Inventor Takashi HAMAYA

Takashi HAMAYA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10381372
    Abstract: Void formation in tungsten lines in a three-dimensional memory device can be prevented by providing polycrystalline aluminum oxide liners in portions of lateral recesses that are laterally spaced from backside trenches by a distance grater than a predefined lateral offset distance. Tungsten nucleates on the polycrystalline aluminum oxide liners prior to nucleating on a metallic liner layer. Thus, tungsten layers can be deposited from the center portion of each backside recess, and the growth of tungsten can proceed toward the backside trenches. By forming the tungsten layers without voids, structural integrity of the three-dimensional memory device can be enhanced.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: August 13, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fumitaka Amano, Takashi Arai, Genta Mizuno, Shigehisa Inoue, Naoki Takeguchi, Takashi Hamaya
  • Publication number: 20180019256
    Abstract: Void formation in tungsten lines in a three-dimensional memory device can be prevented by providing polycrystalline aluminum oxide liners in portions of lateral recesses that are laterally spaced from backside trenches by a distance grater than a predefined lateral offset distance. Tungsten nucleates on the polycrystalline aluminum oxide liners prior to nucleating on a metallic liner layer. Thus, tungsten layers can be deposited from the center portion of each backside recess, and the growth of tungsten can proceed toward the backside trenches. By forming the tungsten layers without voids, structural integrity of the three-dimensional memory device can be enhanced.
    Type: Application
    Filed: October 24, 2016
    Publication date: January 18, 2018
    Inventors: Fumitaka AMANO, Takashi ARAI, Genta MIZUNO, Shigehisa INOUE, Naoki TAKEGUCHI, Takashi HAMAYA
  • Publication number: 20170345629
    Abstract: Reliability of a semiconductor device is improved, and use efficiency of a sputtering apparatus is increased. When depositing thin films over a main surface of a semiconductor wafer using a magnetron sputtering apparatus in which a collimator is installed in a space between the semiconductor wafer and a target installed in a chamber, a region inner than a peripheral part of the collimator is made thinner than the peripheral part. Thus, it becomes possible to suppress deterioration in uniformity of the thin film in a wafer plane, which may occur as the integrated usage of the target increases.
    Type: Application
    Filed: August 21, 2017
    Publication date: November 30, 2017
    Inventors: Takashi HAMAYA, Hideaki TSUGANE, Hidenori SUZUKI
  • Patent number: 9748081
    Abstract: Reliability of a semiconductor device is improved, and use efficiency of a sputtering apparatus is increased. When depositing thin films over a main surface of a semiconductor wafer using a magnetron sputtering apparatus in which a collimator is installed in a space between the semiconductor wafer and a target installed in a chamber, a region inner than a peripheral part of the collimator is made thinner than the peripheral part. Thus, it becomes possible to suppress deterioration in uniformity of the thin film in a wafer plane, which may occur as the integrated usage of the target increases.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: August 29, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Hamaya, Hideaki Tsugane, Hidenori Suzuki
  • Publication number: 20160086779
    Abstract: Reliability of a semiconductor device is improved, and use efficiency of a sputtering apparatus is increased. When depositing thin films over a main surface of a semiconductor wafer using a magnetron sputtering apparatus in which a collimator is installed in a space between the semiconductor wafer and a target installed in a chamber, a region inner than a peripheral part of the collimator is made thinner than the peripheral part. Thus, it becomes possible to suppress deterioration in uniformity of the thin film in a wafer plane, which may occur as the integrated usage of the target increases.
    Type: Application
    Filed: September 22, 2015
    Publication date: March 24, 2016
    Inventors: Takashi HAMAYA, Hideaki TSUGANE, Hidenori SUZUKI
  • Publication number: 20110127158
    Abstract: In a copper damascene wiring process, a tantalum-based laminated film, which is used as a barrier metal film, is continuously formed in a sputtering deposition chamber. When the continuous deposition process is discontinuously applied to a number of wafers, a tantalum film and a tantalum nitride film which are relatively thin are alternately deposited over an inner surface of a shield in a sputter deposition chamber, which results in a thickness of the deposited film being on the order of several thousand nanometers. The deposited film peels off due to internal stress therein to generate foreign material or particles. To counteract this, a tantalum film, which is much thicker than the tantalum film formed over the wafer at one time, is formed over the substantially inner wall of the chamber at predetermined intervals when repeatedly depositing the tantalum nitride film and the tantalum film in the sputtering deposition chamber.
    Type: Application
    Filed: November 5, 2010
    Publication date: June 2, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi HAMAYA, Hidenori SUZUKI, Yuichi HARANO, Masahiko ITO