Patents by Inventor Takashi Hioki

Takashi Hioki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multilayer capacitor, wiring board, decoupling circuit, and high frequency circuit incorporating the same
    Patent number: 6606237
    Abstract: A multilayer capacitor is constructed to minimize equivalent series inductance (ESL) and to achieve large capacitance. The capacitor includes first and second main go surface terminal electrodes provided on a first main surface of the main body of the multilayer capacitor. First and second side surface terminal electrodes are disposed on four side surfaces of the main body. The main body is divided into a low ESL section of the first main-surface side and a high capacitance section of the second main-surface side. In the low ESL section, in addition to first and second low ESL internal electrodes, a first conductive via-hole electrically connecting the first low ESL internal electrode to the first main surface terminal electrode and a second conductive via-hole electrically connecting the second low ESL internal electrode to the second main surface terminal electrode are provided.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: August 12, 2003
    Assignees: Murata Manufacturing Co., Ltd., Intel Corporation
    Inventors: Yasuyuki Naito, Masaaki Taniguchi, Yoichi Kuroda, Haruo Hori, David G. Figueroa, Jorge P. Rodriguez, Nicholas R. Watts, Nicholas L. Holmberg, Takashi Hioki