Abstract: Disclosed is a near-infrared pulsed light source including: a first near-infrared light source to emit near-infrared laser light which is a continuous wave of wavelength longer than 1,240 nm; and a pulse modulator to modulate the near-infrared laser light from the first near-infrared light source with pulses, and to emit, as first near-infrared light, near-infrared pulsed light whose pulse width is less than or equal to one nanosecond, and whose extinction ratio is greater than or equal to a value which is a result of adding 10 dB to a pulse duty ratio (dB) which is a ratio of a pulse width of each of the pulses and a period of the pulses.

Abstract: A write head degaussing circuit and methodology configured to end the degaussing signal a selectable percentage short of the tapered degaussing waveform, starting the degaussing of the write head current Iw at a percentage less than Iw, removing any overshoot of the degaussing signal, and any combination of the above.

Abstract: In a network in which a plurality of terminals share one communication channel, signal collision is avoided and a predetermined signal is transmitted with a higher priority level. Priority levels are defined so that they are common to all the packets to be sent by nodes (including terminals and relating devices) on a network. Respective slots that regulate timing for sending out packets are assigned to the respective priority levels. Each slot is determined with reference to a time at which an ongoing packet transmission on the communication channel has finished. The priority levels are allocated in such a manner that packets having higher priority levels (packets to be sent out with higher priority) are allocated to slots having earlier timing.

Abstract: A house code assigning device includes a communication unit for sending a command for requesting transmission of a house code to electronic equipment included in a system and for receiving a house code from the electronic equipment, a verification unit for verifying whether or not a house code received by the communication unit is correct and for outputting a verification result showing whether or not the house code received by the communication unit is correct, and a display control unit for controlling a light emitting unit according to the verification result from the verification unit.

Abstract: It is an object to automatically and rapidly assign a logical network address to a terminal connected newly to a network. A data holding section (14) of a network terminal (10) holds a value of a self-device address (DA) and information indicating whether the DA has a maximum value in the same network address (NA) or not. When a terminal connected newly to a network transmits address request data for requesting to give an address onto the network, a terminal having the maximum DA at that time transmits DA grant data indicative of a self-address (that is, the maximum DA) as an acknowledgement thereof. A new terminal receiving the DA grant data sets a greater value than the maximum DA to be the self-DA.

Abstract: An internal clock signal, of which a pulse repetition period is half of that of an external clock signal, is produced in a test circuit from the external clock signal and an external clock enabling signal of which a phase is shifted from that of the external clock signal by ¼ of the pulse repetition period of the external clock signal. When an external write command signal set to a low level is received in the test circuit, an internal write command signal, of which a level is risen up in synchronization with a leading edge of the external clock signal, is produced, and a first pre-charge signal, of which a level is risen up in synchronization with a trailing edge of the internal clock signal obtained just after the leading edge of the external clock signal, is produced. Therefore a write recovery time-period equal to ¼ of the pulse repetition period of the external clock signal is obtained from the internal write command signal and the first pre-charge signal.

Abstract: A main memory control system has an initial data generating circuit for generating initial data, an initialization control circuit for activating an initialize signal in response to an initialize command, and a refresh control circuit that generates refresh addresses. When the initialize signal is inactive, the main memory control system performs normal read, write, and refresh operations. When the initialize signal is active, the main memory control system selects the initial data by means of a data multiplexer and performs only write operations, writing the initial data at refresh addresses generated by the refresh control circuit. If the main memory has an interleaved structure, the initial data are written in all banks simultaneously.