Patents by Inventor Takashi Hirotani
Takashi Hirotani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230371266Abstract: A memory device includes a stacked body of alternately arranged conductor-including layers and insulating films in the first direction and pillar bodies within the stacked body. Each pillar body includes first and second conductive pillars and an insulator pillar located between the first conductive pillar and the second conductive pillar. Each conductor-including layer includes a semiconductor member, an electrode film and a ferroelectric layer provided between the semiconductor member and the electrode film. The semiconductor members in the multiple conductor-including layers are separated from each other in the first direction.Type: ApplicationFiled: January 19, 2023Publication date: November 16, 2023Inventors: Minori Kajimoto, Takashi Hirotani, Masahiro Yoshihara
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Publication number: 20220238536Abstract: A memory device includes source-drain structure bodies and gate structure bodies arranged along a first direction, and global word lines. The source-drain structure body includes a bit line, and first to third semiconductor layers. The first and second semiconductor layers are of first conductivity type and the first semiconductor layer is connected to the bit line. The third semiconductor layer of a second conductivity type contacts the first and second semiconductor layers. The gate structure body includes a local word line and a charge storage film. A first source-drain structure body includes a bit line forming a first reference bit line. A first global word line connects to the local word lines in the gate structure bodies formed on both sides of the first reference bit line and to the local word lines formed in alternate gate structure bodies that are formed between the remaining plurality of source-drain structure bodies.Type: ApplicationFiled: January 14, 2022Publication date: July 28, 2022Inventors: Yosuke Nosho, Takashi Ohashi, Shohei Kamisaka, Takashi Hirotani
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Patent number: 11264102Abstract: A semiconductor storage device includes a bit line driver, and a control circuit configured to be able to execute a writing sequence for repeating at least one loop including a program operation for writing data into at least one of the plurality of memory cells and a verify operation for verifying the data a plurality of times while increasing a program voltage by a step-up voltage. The bit line driver can obtain a number of memory cells into which writing is completed or a number of memory cells into which writing is insufficient for each of the at least two consecutive loops from a result of the verify operation, and the control circuit can determine the step-up voltage in the subsequent loop based on a result obtained by the bit line driver.Type: GrantFiled: August 31, 2020Date of Patent: March 1, 2022Assignee: Kioxia CorporationInventors: Kiichi Tachi, Takashi Hirotani
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Publication number: 20210125673Abstract: A semiconductor storage device includes a bit line driver, and a control circuit configured to be able to execute a writing sequence for repeating at least one loop including a program operation for writing data into at least one of the plurality of memory cells and a verify operation for verifying the data a plurality of times while increasing a program voltage by a step-up voltage. The bit line driver can obtain a number of memory cells into which writing is completed or a number of memory cells into which writing is insufficient for each of the at least two consecutive loops from a result of the verify operation, and the control circuit can determine the step-up voltage in the subsequent loop based on a result obtained by the bit line driver.Type: ApplicationFiled: August 31, 2020Publication date: April 29, 2021Applicant: Kioxia CorporationInventors: Kiichi TACHI, Takashi HIROTANI
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Patent number: 10249641Abstract: A semiconductor memory device according to one embodiment includes a substrate, a stacked body provided on a first-direction side of the substrate, a semiconductor member extending in the first direction, and a charge storage film provided between the stacked body and the semiconductor member. The stacked body includes first insulating films and electrode films stacked alternately along the first direction. A recess is made in a surface of the stacked body facing the semiconductor member every one of the electrode films.Type: GrantFiled: September 7, 2016Date of Patent: April 2, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takashi Hirotani, Minori Kajimoto
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Patent number: 9911752Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a stacked body provided on the semiconductor substrate and including a plurality of electrode films being disposed to be separated from each other along a vertical direction, a first semiconductor member provided inside the stacked body and contacting the semiconductor substrate, a second semiconductor member provided on the first semiconductor member inside the stacked body, contacting the first semiconductor member and extending in the vertical direction, and an insulating film provided between the second semiconductor member and the electrode films. A configuration of a contact surface between the first semiconductor member and the second semiconductor member is convex downward.Type: GrantFiled: August 1, 2016Date of Patent: March 6, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takayuki Kashima, Masahiro Fukuda, Takashi Hirotani
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Publication number: 20170271355Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a stacked body provided on the semiconductor substrate and including a plurality of electrode films being disposed to be separated from each other along a vertical direction, a first semiconductor member provided inside the stacked body and contacting the semiconductor substrate, a second semiconductor member provided on the first semiconductor member inside the stacked body, contacting the first semiconductor member and extending in the vertical direction, and an insulating film provided between the second semiconductor member and the electrode films. A configuration of a contact surface between the first semiconductor member and the second semiconductor member is convex downward.Type: ApplicationFiled: August 1, 2016Publication date: September 21, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Takayuki KASHIMA, Masahiro FUKUDA, Takashi HIROTANI
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Publication number: 20170236827Abstract: A semiconductor memory device according to one embodiment includes a substrate, a stacked body provided on a first-direction side of the substrate, a semiconductor member extending in the first direction, and a charge storage film provided between the stacked body and the semiconductor member. The stacked body includes first insulating films and electrode films stacked alternately along the first direction. A recess is made in a surface of the stacked body facing the semiconductor member every one of the electrode films.Type: ApplicationFiled: September 7, 2016Publication date: August 17, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Takashi HIROTANI, Minori KAJIMOTO
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Patent number: 9142774Abstract: According to one embodiment, a nonvolatile memory device includes a first electrode, a second electrode, and a memory cell provided between the first electrode and the second electrode. The memory cell includes a retention unit, a resistance change unit, and an ion supply unit. The retention unit is provided on the first electrode and has an electron trap. The resistance change unit is provided on the retention unit. The ion supply unit is provided between the resistance change unit and the second electrode and includes a metal element.Type: GrantFiled: December 14, 2012Date of Patent: September 22, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hidehiko Yabuhara, Takashi Hirotani, Junji Kataoka, Hisashi Kameoka
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Publication number: 20130153850Abstract: According to one embodiment, a nonvolatile memory device includes a first electrode, a second electrode, and a memory cell provided between the first electrode and the second electrode. The memory cell includes a retention unit, a resistance change unit, and an ion supply unit. The retention unit is provided on the first electrode and has an electron trap. The resistance change unit is provided on the retention unit. The ion supply unit is provided between the resistance change unit and the second electrode and includes a metal element.Type: ApplicationFiled: December 14, 2012Publication date: June 20, 2013Inventors: Hidehiko Yabuhara, Takashi Hirotani, Junji Kataoka, Hisashi Kameoka