Patents by Inventor Takashi Hisada

Takashi Hisada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180294213
    Abstract: A via structure for electric connection is disclosed. The via structure includes a substrate that has a first surface and a via hole opened to the first surface. The via structure includes also a stress buffer layer disposed on the first surface of the substrate, which has an opening aligned to the via hole of the substrate. The via structure further includes a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate. In the via structure, the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.
    Type: Application
    Filed: April 6, 2017
    Publication date: October 11, 2018
    Inventors: Toyohiro Aoki, Takashi Hisada, Akihiro Horibe, Sayuri Hada, Eiji I. Nakamura, Kuniaki Sueoka
  • Publication number: 20180277509
    Abstract: Methods for depositing material on a chip include forming a mold layer. The mold layer includes one or more openings over respective contact areas, each of the one or more openings having an upper volume and a lower volume. The upper volume has a smaller diameter than a diameter of the lower volume. Each contact area is within the respective lower volume. A material is injected into the one or more openings under pressure.
    Type: Application
    Filed: May 24, 2018
    Publication date: September 27, 2018
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji Nakamura, Kuniaki Sueoka
  • Publication number: 20180269173
    Abstract: Wafers include multiple bulk redistribution layers. A contact pad is formed on a surface of one of the bulk redistribution layers. A final redistribution layer is formed on the surface and in contact with the contact pad. Solder is formed on the contact pad. The solder includes a pedestal portion formed to a same height as the final redistribution layer and a ball portion above the pedestal portion.
    Type: Application
    Filed: May 23, 2018
    Publication date: September 20, 2018
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji I. Nakamura
  • Publication number: 20180259729
    Abstract: An optical structure includes a substrate including a cavity on a first surface of the substrate, an optical component on the substrate and an adhesive applied to a side of the optical component to fix the optical component to the substrate. The optical component includes a recess on a second surface of the optical component, the second surface is opposed to the first surface of the substrate, and the recess is provided along an edge of the second surface.
    Type: Application
    Filed: April 9, 2018
    Publication date: September 13, 2018
    Inventors: Elaine Cyr, Paul F. Fortier, Takashi Hisada, Patrick Jacques, Koji Masuda, Masao Tokunari
  • Publication number: 20180259728
    Abstract: An optical structure includes a substrate including a cavity on a first surface of the substrate, an optical component on the substrate and an adhesive applied to a side of the optical component to fix the optical component to the substrate. The optical component includes a recess on a second surface of the optical component, the second surface is opposed to the first surface of the substrate, and the recess is provided along an edge of the second surface.
    Type: Application
    Filed: September 12, 2017
    Publication date: September 13, 2018
    Inventors: Elaine Cyr, Paul F. Fortier, Takashi Hisada, Patrick Jacques, Koji Masuda, Masao Tokunari
  • Patent number: 10037967
    Abstract: Methods for depositing material on a chip include forming a mold layer on a substrate. The mold layer has one or more openings over respective contact areas on the substrate. The one or more openings are formed from an upper volume and a lower volume, the upper volume having a smaller diameter than a diameter of the lower volume. A material is injected into the one or more openings under pressure, such that gas trapped in the one or more openings displaces into the lower volume until the injected material in the one or more openings makes contact with each respective contact area.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: July 31, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji Nakamura, Kuniaki Sueoka
  • Patent number: 10037958
    Abstract: Wafers include multiple bulk redistribution layers. A terminal contact pad is on a surface of one of the bulk redistribution layers. A final redistribution layer is formed on the surface and in contact with the terminal contact pad. The final redistribution layer is formed from a material other than a material of the plurality of bulk redistribution layers. A solder ball is formed on the terminal contact pad.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: July 31, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji I. Nakamura
  • Patent number: 9989713
    Abstract: An optical structure includes a substrate including a cavity on a first surface of the substrate, an optical component on the substrate and an adhesive applied to a side of the optical component to fix the optical component to the substrate. The optical component includes a recess on a second surface of the optical component, the second surface is opposed to the first surface of the substrate, and the recess is provided along an edge of the second surface.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: June 5, 2018
    Assignee: International Business Machines Corporation
    Inventors: Elaine Cyr, Paul F. Fortier, Takashi Hisada, Patrick Jacques, Koji Masuda, Masao Tokunari
  • Patent number: 9957193
    Abstract: A single glass panel for a fire door and a double glazed glass panel for a fire door that have a fireproofness with which the glass sheet passes an international standard ISO 0834 flame insulating performance test and are as inexpensive as possible. For example, the single glass panel for a fire door is obtained by forming a heat reflecting coating with a low emissivity on at least one surface of a glass sheet that is a heat strengthened glass sheet or is more thermally strengthened than a heat strengthened glass sheet, and the double glazed glass panel for a fire door includes a first glass sheet (2B) obtained by forming a heat reflecting coating (4) with an emissivity of 0.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: May 1, 2018
    Assignee: Nippon Sheet Glass Company, Limited
    Inventors: Takashi Hisada, Kazuyuki Suzuki, Sachiko Nishikawa, Takashi Yokota
  • Publication number: 20180108630
    Abstract: Wafers include multiple bulk redistribution layers. A terminal contact pad is on a surface of one of the bulk redistribution layers. A final redistribution layer is formed on the surface and in contact with the terminal contact pad. The final redistribution layer is formed from a material other than a material of the plurality of bulk redistribution layers. A solder ball is formed on the terminal contact pad.
    Type: Application
    Filed: June 16, 2017
    Publication date: April 19, 2018
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji Nakamura
  • Publication number: 20180108631
    Abstract: Wafers and methods of forming solder balls include etching a hole in a final redistribution layer over a terminal contact pad on a wafer to expose the terminal contact pad. Solder is injected into the hole using an injection nozzle that is in direct contact with the final redistribution layer. The final redistribution layer is etched back. The injected solder is reflowed to form a solder ball.
    Type: Application
    Filed: October 2, 2017
    Publication date: April 19, 2018
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji Nakamura
  • Publication number: 20180076164
    Abstract: A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.
    Type: Application
    Filed: April 27, 2017
    Publication date: March 15, 2018
    Inventors: Toyohiro Aoki, Takashi Hisada, Hiroyuki Mori, Eiji Nakamura, Yasumitsu Orii
  • Publication number: 20180076165
    Abstract: A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.
    Type: Application
    Filed: September 25, 2017
    Publication date: March 15, 2018
    Inventors: Toyohiro Aoki, Takashi Hisada, Hiroyuki Mori, Eiji Nakamura, Yasumitsu Orii
  • Publication number: 20180076163
    Abstract: A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.
    Type: Application
    Filed: September 14, 2016
    Publication date: March 15, 2018
    Inventors: Toyohiro Aoki, Takashi Hisada, Hiroyuki Mori, Eiji Nakamura, Yasumitsu Orii
  • Publication number: 20180061796
    Abstract: A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer.
    Type: Application
    Filed: July 26, 2017
    Publication date: March 1, 2018
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji I. Nakamura
  • Publication number: 20180061797
    Abstract: A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer.
    Type: Application
    Filed: November 3, 2017
    Publication date: March 1, 2018
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji I. Nakamura
  • Patent number: 9859241
    Abstract: A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji I Nakamura
  • Patent number: 9837367
    Abstract: Wafers and methods of forming solder balls include forming a final redistribution layer over terminal contact pad on a surface of a wafer. The wafer includes multiple bulk redistribution layers. A hole is etched in the final redistribution layer to expose the terminal contact pad. Solder is injected into the hole using an injection nozzle that is in direct contact with the final redistribution layer. The final redistribution layer is etched back. The injected solder is reflowed to form a solder ball.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: December 5, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji I. Nakamura
  • Patent number: 8952551
    Abstract: A semiconductor package includes a wiring substrate, a semiconductor chip, and a conductor plate in order to reduce a voltage drop at the central portion of a chip caused by wiring resistance from a peripheral connection pad disposed on the periphery of the chip. Central electrode pads for use in ground/power-supply are disposed on the central portion of the chip. The conductor plate for use in ground/power-supply is disposed on the chip such that an insulating layer is disposed therebetween. The central electrode pads on the chip and the conductor plate are connected together by wire bonding through an opening formed in the insulating layer and the conductor plate. An extraction portion of the conductor plate is connected to a power-supply wiring pad on the wiring substrate. Preferably, the conductor plate is composed of a multilayer structure, and each conductor plate is used in power-supply wiring or ground wiring.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Takashi Hisada, Katsuyuki Yonehara
  • Publication number: 20140248447
    Abstract: A single glass panel for a fire door and a double glazed glass panel for a fire door that have a fireproofness with which the glass sheet passes an international standard ISO 0834 flame insulating performance test and are as inexpensive as possible. For example, the single glass panel for a fire door is obtained by forming a heat reflecting coating with a low emissivity on at least one surface of a glass sheet that is a heat strengthened glass sheet or is more thermally strengthened than a heat strengthened glass sheet, and the double glazed glass panel for a fire door includes a first glass sheet (2B) obtained by forming a heat reflecting coating (4) with an emissivity of 0.
    Type: Application
    Filed: October 29, 2012
    Publication date: September 4, 2014
    Applicant: Nippon Sheet Glass Company, Limited
    Inventors: Takashi Hisada, Kazuyuki Suzuki, Sachiko Nishikawa, Takashi Yokota