Abstract: In at least some implementations, a fuel metering valve, includes a bobbin defining a passage and having one or more voids in the surface of the bobbin that defines the passage, aa wire coil around the bobbin and an armature. The armature is received within the passage in the bobbin and movable relative to the bobbin from a first position to a second position when electricity is supplied to the wire coil.

Abstract: In at least some implementations, a fuel metering valve, includes a bobbin defining a passage and having one or more voids in the surface of the bobbin that defines the passage, aa wire coil around the bobbin and an armature. The armature is received within the passage in the bobbin and movable relative to the bobbin from a first position to a second position when electricity is supplied to the wire coil.

Abstract: In at least some implementations, a charge forming device for a combustion engine includes a throttle body and a throttle valve. The throttle body has a throttle bore with an inlet through which air flows into the throttle bore and an outlet from which a fuel and air mixture exits the throttle bore. The throttle bore has a throat between the inlet and outlet and the throat has a reduced flow area compared to at least one of the inlet and outlet. The throttle valve has a valve head received within the throat of the throttle bore and movable relative to the throttle body between a first position and a second position wherein the flow area between the valve head and the throttle body is greater when the valve head is in the second position than in the first position.

Abstract: In at least some implementations, a charge forming system for a combustion engine includes a first fuel supply device having a first passage from which fuel is discharged for delivery to the engine and a second fuel supply device having a second passage from which fuel is discharged for delivery to the engine. The first passage communicates with the second passage so that the fuel in the first passage is combined with the fuel in the second passage.

Abstract: In at least some implementations, a charge forming system for a combustion engine includes a first fuel supply device having a first passage from which fuel is discharged for delivery to the engine and a second fuel supply device having a second passage from which fuel is discharged for delivery to the engine. The first passage communicates with the second passage so that the fuel in the first passage is combined with the fuel in the second passage.

Abstract: In at least some implementations, a charge forming device for a combustion engine includes a throttle body and a throttle valve. The throttle body has a throttle bore with an inlet through which air flows into the throttle bore and an outlet from which a fuel and air mixture exits the throttle bore. The throttle bore has a throat between the inlet and outlet and the throat has a reduced flow area compared to at least one of the inlet and outlet. The throttle valve has a valve head received within the throat of the throttle bore and movable relative to the throttle body between a first position and a second position wherein the flow area between the valve head and the throttle body is greater when the valve head is in the second position than in the first position.

Abstract: Provided is a lock management system, a lock management method and a lock management program whereby lock acquisition and release processes can be carried out at high speed. A lock management system 1 having a multiprocessor includes: a lock acquisition process 310 for carrying out a lock acquisition process for a thread according to one or more lock modes, at least a portion of the lock modes being a shared lock that can be acquired by one or more threads; and lock status holding means 410 for managing the number of threads acquiring a lock, by first information which can express the number of threads by one word that can be handled by an indivisible access command of the multi-processor, and second information representing a whole range of the number of threads that can possibly acquire a lock in each lock mode.

Abstract: In a method which analyzes system behavior using performance indices related to time, a program portion that has become a bottleneck is discovered; however, discovery is not made back to the cause of the same. This bottleneck detection method, when varying a load to measure behavior of a system, performs measurement regarding a plurality of performance indices. Then by analyzing the results of the same by way of analysis unit, program portions that are bottlenecks are identified, and causes of the program portions being bottlenecks are identified.

Abstract: A processor unit (200) includes: cache memory (210); an instruction execution unit (220); a processing unit (230) that detects fact that a thread enters an exclusive control section which is specified in advance to become a bottleneck; a processing unit (240) that detects a fact that the thread exits the exclusive control section; and an execution flag (250) that indicates whether there is the thread that is executing a process in the exclusive control section based on detection results. The cache memory (210) temporarily stores a priority flag in each cache entry, and the priority flag indicates whether data is to be used during execution in the exclusive control section. When the execution flag (250) is set, the processor unit (200) sets the priority flag that belongs to an access target of cache entries. The processor unit (200) leaves data used in the exclusive control section in the cache memory by determining a replacement target of cache entries using the priority flag when a cache miss occurs.

Abstract: A processor unit (200) includes: cache memory (210); an instruction execution unit (220); a processing unit (230) that detects fact that a thread enters an exclusive control section which is specified in advance to become a bottleneck; a processing unit (240) that detects a fact that the thread exits the exclusive control section; and an execution flag (250) that indicates whether there is the thread that is executing a process in the exclusive control section based on detection results. The cache memory (210) temporarily stores a priority flag in each cache entry, and the priority flag indicates whether data is to be used during execution in the exclusive control section. When the execution flag (250) is set, the processor unit (200) sets the priority flag that belongs to an access target of cache entries. The processor unit (200) leaves data used in the exclusive control section in the cache memory by determining a replacement target of cache entries using the priority flag when a cache miss occurs.

Abstract: A processor unit (200) includes: cache memory (210); an instruction execution unit (220); a processing unit (230) that detects fact that a thread enters an exclusive control section which is specified in advance to become a bottleneck; a processing unit (240) that detects a fact that the thread exits the exclusive control section; and an execution flag (250) that indicates whether there is the thread that is executing a process in the exclusive control section based on detection results. The cache memory (210) temporarily stores a priority flag in each cache entry, and the priority flag indicates whether data is to be used during execution in the exclusive control section. When the execution flag (250) is set, the processor unit (200) sets the priority flag that belongs to an access target of cache entries. The processor unit (200) leaves data used in the exclusive control section in the cache memory by determining a replacement target of cache entries using the priority flag when a cache miss occurs.

Abstract: A data storage device includes: a storing unit which stores means for storing a counter associated with each hash entry in a hash table; a first executing unit which means for, when receiving an execution command for a process, increments or decrements incrementing or decrementing a value of the counter which is associated with the hash entry according to an operation for the hash entry, the operation being included in the process; and a second executing unit which means for, when receiving an execution command for a process including an deletion operation for the hash entry, executes executing the deletion operation for the hash entry according to the value of the counter which is associated with the hash entry.

Abstract: In a method which analyzes system behavior using performance indices related to time, a program portion that has become a bottleneck is discovered; however, discovery is not made back to the cause of the same. This bottleneck detection method, when varying a load to measure behavior of a system, performs measurement regarding a plurality of performance indices. Then by analyzing the results of the same by way of analysis unit, program portions that are bottlenecks are identified, and causes of the program portions being bottlenecks are identified.

Abstract: A technique for identifying conflicting sub-processes easily in a computer system that processes a plurality of transactions in parallel is provided. In a conflicting sub-process identification method according to the present invention, a comparison is made between processing time periods for which transactions executed in parallel have conflicting parts and for which transactions executed in parallel do not have conflicting parts. This comparison is made for a plurality of transaction processing programs each comprising a plurality of sub-processes. Then, on the basis of correspondence relationships between performance indices obtained from the comparison result, conflicting combination of sub-processes competing for a resource are identified.

Abstract: Provided is a lock management system, a lock management method and a lock management program whereby lock acquisition and release processes can be carried out at high speed. A lock management system 1 having a multiprocessor includes: a lock acquisition process 310 for carrying out a lock acquisition process for a thread according to one or more lock modes, at least a portion of the lock modes being a shared lock that can be acquired by one or more threads; and lock status holding means 410 for managing the number of threads acquiring a lock, by first information which can express the number of threads by one word that can be handled by an indivisible access command of the multi-processor, and second information representing a whole range of the number of threads that can possibly acquire a lock in each lock mode.

Abstract: Provided is an information processing apparatus. The information processing apparatus includes thread control means for, at starting a plurality of threads, giving an identifier to the thread, and, at ending the each thread, notifying of an end along with the identifier; and data element control means for, in case that a deletion thread which deletes a data element from list-structured data being executed, maintaining a content of the deleted data element in an unmodifiable state until ends of all the threads which started before the deletion processing by the deletion thread being confirmed by a notification of the end along with the identifier, and, in case that the ends of all the threads which started before the deletion processing by the deletion thread being notified of along with the identifier, putting the deleted data element into a reusable state.

Abstract: A log record writing system includes a log writing media 1, a log writing control unit 2 which manages writing operation of a log record according to a log sequence number which is sequentially increased and writes the log record in the log writing media, and a queue storing unit 3 which stores a queue used so as to select a process which is an object for the waking-up operation among the processes which are waiting for completion of writing the log record in a sleeping state, and keeps the entries, which are elements of the queue, including process information and log sequence operation of the log record is performed by the other process, the log writing control unit 2 stores the queue entry that sets the log sequence number and the first process information and puts the first process to be in a sleeping state, and when the log record is completely written, the log writing control unit 2 compares the log sequence number included in an entry stored in the queue with a log sequence number of the log record whi

Abstract: A multiprocessor system includes first through third processors and memory storing address data, all interconnected. In the first processor an access control unit receives the address and the data, and a cache memory storing a cache line including the address, the data and a validity flag. The cache memory invalidates the flag when receiving a request for invalidating the cache line. The access control unit stores the address as a monitoring target when the flag of the cache line is invalidated. When storing a first address included in an invalidated first cache line as a monitoring target, receiving a second address and second data outputted by the third processor is output in response to a request of the second processor, the access control unit judges whether the first address coincides with the second address and relates the first address to the second address to store them when true.

Abstract: When a process sleep event, a process wake-up event, a process save event, and a process resume event occur in an IT system having a multiprocessor configuration, a tracer respectively generates sleep event data, wake-up event data, save event data, and resume event data and records them as trace data in a trace buffer. The analysis unit generates an analysis result by referring to the trace data to accumulate a number of times of execution of the process wake-up process and a first time as a time from the process save event to the process wake-up event or to the process resume event with respect to a plurality of processes to be executed. When a contention for a shared resource occurs, the process wake-up process is repeatedly executed among relevant processes. For this reason, based on the analysis result, a possibility can be presented that the shared resource contention occurs in the IT system.

Abstract: A processor unit (200) includes: cache memory (210); an instruction execution unit (220); a processing unit (230) that detects fact that a thread enters an exclusive control section which is specified in advance to become a bottleneck; a processing unit (240) that detects a fact that the thread exits the exclusive control section; and an execution flag (250) that indicates whether there is the thread that is executing a process in the exclusive control section based on detection results. The cache memory (210) temporarily stores a priority flag in each cache entry, and the priority flag indicates whether data is to be used during execution in the exclusive control section. When the execution flag (250) is set, the processor unit (200) sets the priority flag that belongs to an access target of cache entries. The processor unit (200) leaves data used in the exclusive control section in the cache memory by determining a replacement target of cache entries using the priority flag when a cache miss occurs.