Patents by Inventor Takashi Ibi

Takashi Ibi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8476814
    Abstract: A light utilization efficiency of a high-pressure discharge lamp is improved even in a case of reducing the size of a reflection mirror without using an auxiliary reflection mirror. In a lamp device where a portion of lights emitted from a discharge bulb to the periphery thereof in forward and backward directions for a predetermined range of angle is reflected at a concave reflection mirror and illuminated to a light collection area of a predetermined size formed forward of the lamp, a prism surface having an angle of refracting or deflecting at least a portion of lights emitted from the discharge bulb that is not reflected at the concave reflection mirror to the light collection area is formed to the outer peripheral surface of the discharge bulb.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: July 2, 2013
    Assignees: Iwasaki Electric Co., Ltd., Fujii Optical Co., Ltd.
    Inventors: Takashi Ibi, Sumio Uehara, Kyouichi Maseki, Yosuke Kano, Toshitaka Higuchi
  • Publication number: 20120300320
    Abstract: A method for manufacturing a lens unit including the steps of: forming a first lens array, having plural first lens sections and first reference surfaces formed in a predetermined arrangement, via glass forming by arranging a glass material between a first assembled molds and by clamping the molds; forming a second lens array, having plural second lens sections and second reference surfaces formed in a predetermined arrangement, via glass forming by arranging a glass material between a second assembled molds and by clamping the molds; forming a third lens array by stacking and bonding the first and second lens arrays so that an optical axis of each lens section of the first and second lens arrays coincide, by using the first and second reference surfaces; and cutting the third lens array into each lens unit which includes at least each one of the first and the second lens sections.
    Type: Application
    Filed: February 1, 2011
    Publication date: November 29, 2012
    Inventors: Hiroyuki Matsuda, Takashi Ibi, Kenichi Iwaida, Shunichi Hayamizu
  • Publication number: 20110260600
    Abstract: A light utilization efficiency of a high-pressure discharge lamp is improved even in a case of reducing the size of a reflection mirror without using an auxiliary reflection mirror. In a lamp device where a portion of lights emitted from a discharge bulb to the periphery thereof in forward and backward directions for a predetermined range of angle is reflected at a concave reflection mirror and illuminated to a light collection area of a predetermined size formed forward of the lamp, a prism surface having an angle of refracting or deflecting at least a portion of lights emitted from the discharge bulb that is not reflected at the concave reflection mirror to the light collection area is formed to the outer peripheral surface of the discharge bulb.
    Type: Application
    Filed: December 3, 2008
    Publication date: October 27, 2011
    Applicants: FUJII OPTICAL CO., LTD., IWASAKI ELECTRIC CO., LTD.
    Inventors: Takashi Ibi, Sumio Uehara, Kyouichi Maseki, Yosuke Kano, Toshitaka Higuchi
  • Patent number: 5619679
    Abstract: A memory control device and method receives a request to transfer a series of first-unit K byte (for example, 512) data in an address space, divides the first-unit K into second-unit L (for example, 64), assigns priority levels to the second-unit L, issues plural times a data transfer instruction to transfer the L-byte data to a memory device comprising a plurality of memories operable in a consecutive access mode, and thus accesses memories in response to the request to transfer the K-byte data. The L-byte data are sequentially allocated in third units S (for example, 64) specified by the data transfer instruction to the memories. The third unit is equal to L or is obtained by dividing L, and is a multiple of an activation unit of the memories. The S-byte data are accessed in the allocated memories in the consecutive access mode.
    Type: Grant
    Filed: February 28, 1995
    Date of Patent: April 8, 1997
    Assignee: Fujitsu Limited
    Inventor: Takashi Ibi
  • Patent number: 5206942
    Abstract: Partial-store access in which a portion of data is changed, is performed using a plurality of memory banks in a memory unit. The partial store-access is performed through an interleave method in which read-data which is one word in length is read from the memory banks during an access time. The one word write-data including a portion of data which is to be changed, is registered in store-data registers. The portion of data is changed in an overwriting operation within the access time. When more than one portion of data is to be changed, such portion is also changed within the access time, but within a different register (i.e., at a later time) than the portion of the storing data initially changed. A positional signal indicating the position of the storing data which is to be changed, is stored in position-signal registers.
    Type: Grant
    Filed: March 8, 1990
    Date of Patent: April 27, 1993
    Assignee: Fujitsu Limited
    Inventor: Takashi Ibi
  • Patent number: 5033001
    Abstract: An apparatus for reading data from a memory in a computer system includes: an address register for holding an address to be supplied to the memory, a read data register for holding data read out from the memory and a device for generating a gated clock signal from a free-running clock signal having a predetermined constant period of time. The gated clock signal is free-running with the predetermined constant period of time in a normal clock mode but is generated by a single pulse with an interval longer than the period of the free-running clock signal in a single clock mode. A device, having serially connected plural registers for shifting a trigger signal in accordance with the free-running clock signal generates a read data clock signal. The trigger signal has a same timing synchronized with a specific phase of the gated clock signal at which a phase of the address register is switched to hold a new address to be supplied to the memory.
    Type: Grant
    Filed: December 18, 1987
    Date of Patent: July 16, 1991
    Assignee: Fujitsu Limited
    Inventor: Takashi Ibi
  • Patent number: 4631725
    Abstract: An error correcting and detecting system using a parity check H-matrix divided into a plurality of block vectors each including four or three column vectors each having eight elements. In the H-matrix, (i) there are no all "0" vectors; (ii) all column vectors are different from each other; (iii) 8 column vectors each having only one "1" is included therein, (iv) each column vector has an odd number of "1's"; (v) the modulo-2 sum of any three column vectors within any block never equals any column vectors of the H-matrix; (vi) the modulo-2 sum of four column vectors within any block never equals an all "0" vector; and (vii) the modulo-2 sum of eight column vectors within any two blocks never equals an all "0" vector.
    Type: Grant
    Filed: December 27, 1984
    Date of Patent: December 23, 1986
    Assignee: Fujitsu Limited
    Inventors: Moriyuki Takamura, Shigeru Mukasa, Takashi Ibi