Abstract: A remote control device includes a light source for irradiating an instruction beam in a non-visible wave length range, and an operation unit for controlling the light source to irradiate the instruction beam when the operation unit is operated. An instruction beam detection apparatus includes an image capturing unit for capturing an image of the instruction beam irradiated from the light source of the remote control device within a detection range thereof; a storage unit for storing a first image captured with the image capturing unit; and a detection unit for detecting a position of the instruction beam on a second image according to a differential image between the first image stored in the storage unit and the second image newly captured with the image capturing unit.

Abstract: Extracting information corresponding to a three-dimensional object from an image captured by plural imaging apparatuses is implemented with simple configuration and processing. Parallax information representing a parallax amount in the X direction of a pair of images captured by a pair of imaging apparatuses disposed at different horizontal positions is stored in a storage section, and a parallax correction control section reads out a parallax amount corresponding to a Y coordinate value of image data for one line input from a pre-image processing unit from the storage section and outputs a selection signal to selectors such that the output of one image data is delayed by the differential amount. A differential image generation unit calculates an absolute value of the differential of the pair of input image data for each pixel and outputs the result as a differential image for detecting the three-dimensional object.

Abstract: A remote control device includes a light source for irradiating an instruction beam in a non-visible wave length range, and an operation unit for controlling the light source to irradiate the instruction beam when the operation unit is operated. An instruction beam detection apparatus includes an image capturing unit for capturing an image of the instruction beam irradiated from the light source of the remote control device within a detection range thereof; a storage unit for storing a first image captured with the image capturing unit; and a detection unit for detecting a position of the instruction beam on a second image according to a differential image between the first image stored in the storage unit and the second image newly captured with the image capturing unit.

Abstract: A semiconductor device includes diffusion layers formed in a SOI layer under a side-wall, a channel formed between the diffusion layers, silicide layers sandwiching the diffusion layers wherein interface junctions between the diffusion layers and the silicide layers are (111) silicon planes.

Abstract: Extracting information corresponding to a three-dimensional object from an image captured by plural imaging apparatuses is implemented with a simple configuration and a simple processing. Parallax information representing a parallax amount in the X direction of a pair of images captured by a pair of imaging apparatuses disposed at different horizontal positions is stored in a storage section 44, and a parallax correction control section 42 reads out a parallax amount corresponding to a Y coordinate value of image data for one line input from a pre-image processing unit 14 from the storage section 44 and outputs a selection signal to selectors 38 and 44 such that the output of one image data is delayed by the differential amount. A differential image generation unit 18 calculates an absolute value of the differential of the pair of input image data for each pixel and outputs the result as a differential image for detecting the three-dimensional object.

Abstract: A semiconductor device includes diffusion layers formed in a SOI layer under a side-wall, a channel formed between the diffusion layers, silicide layers sandwiching the diffusion layers wherein interface junctions between the diffusion layers and the silicide layers are (111) silicon planes.

Abstract: A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces of source and drain regions. A ratio of the metal to the silicon in the metallic silicide layers is X to Y. A ratio of the metal to the silicon of metallic silicide having the lowest resistance among stoichiometric metallic silicides is X0 to Y0. X, Y, X0 and Y0 satisfy the following inequality: (X/Y)>(X0/Y0).

Abstract: A memory cell structure comprises a first memory capacitor that is arranged in a first local area, and includes a first lower electrode, a first upper electrode, and a first dielectric oxide film interposed between the first lower electrode and the first upper electrode; a second memory capacitor that is spaced apart from the first memory capacitor and arranged in the first local area, and includes a second lower electrode, a second upper electrode, and a second dielectric oxide film interposed between the second lower electrode and the second upper electrode; and a first local interconnection layer.

Abstract: A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces of a source and a drain regions. A ratio of the metal to the silicon in the metallic silicide layers is X to Y. A ratio of the metal to the silicon of metallic silicide having the lowest resistance among stoichiometaric metallic silicides is X0 to Y0. X, Y, X0 and Y0 satisfy the following inequity: (X/Y)>(X0/Y0).

Abstract: A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces of source and drain regions. A ratio of the metal to the silicon in the metallic silicide layers is X to Y. A ratio of the metal to the silicon of metallic silicide having the lowest resistance among stoichiometric metallic silicides is X0 to Y0. X, Y, X0 and Y0 satisfy the following inequality: (X/Y)>(X0/Y0).

Abstract: A memory cell structure comprises a first memory capacitor that is arranged in a first local area, and includes a first lower electrode, a first upper electrode, and a first dielectric oxide film interposed between the first lower electrode and the first upper electrode; a second memory capacitor that is spaced apart from the first memory capacitor and arranged in the first local area, and includes a second lower electrode, a second upper electrode, and a second dielectric oxide film interposed between the second lower electrode and the second upper electrode; and a first local interconnection layer.

Abstract: A semiconductor device includes diffusion layers formed in a SOI layer under a side-wall, a channel formed between the diffusion layers, silicide layers sandwiching the diffusion layers wherein interface junctions between the diffusion layers and the silicide layers are (111) silicon planes.

Abstract: A ferroelectric memory which ensures a high reliability without increasing the area of a capacitor, and a method of manufacturing the same. An interlayer film 4 is formed on a semiconductor substrate 1 which has been formed with a circuit including a transistor 2 for storage element selection, and a contact hole is formed through the interlayer insulating film 4 by a plasma etching method using an etching gas including CHF3. Consequently, the resulting contact hole is formed wider toward the ferroelectric capacitor 10 and narrower toward a diffusion layer 2a of the transistor 2. When an electrically conductive material such as tungsten is filled in the contact hole, a material gas is evenly supplied into the contact hole, thereby preventing a void, called a “seam,” in a central region. Thus, the surface of a cell plug can be finished with a uniform and flat surface, and a ferroelectric capacitor 10 having good characteristics can be formed on the cell plug 20.

Abstract: A heat treatment for diffusing impurity ions implanted into a silicon layer is performed at a heat treatment temperature which is less than an aggregation temperature of the silicon layer. A thermal aggregation of the silicon layer can be inhibited, thereby reducing a silicon deficiency of the silicon layer.

Abstract: According to the ferroelectric device of the present invention, the crystalline structure in the ferroelectric film is improved and the physical characteristics of the ferroelectric device can improve.

Abstract: A device isolation region made up of a silicon oxide film, which is perfectly isolated up to the direction of the thickness of an SOI silicon layer, and an activation region of the SOI silicon layer, whose only ends are locally thinned, are formed on an SOI substrate. A source diffusion layer and a drain diffusion layer of a MOS field effect transistor in the activation region are provided so that according to the silicidization of the SOI silicon layer subsequent to the formation of a high melting-point metal, a Schottky junction is formed only at each end of the activation region and a PN junction is formed at a portion other than each end thereof.

Abstract: A device isolation region made up of a silicon oxide film, which is perfectly isolated up to the direction of the thickness of an SOI silicon layer, and an activation region of the SOI silicon layer, whose only ends are locally thinned, are formed on an SOI substrate. A source diffusion layer and a drain diffusion layer of a MOS field effect transistor in the activation region are provided so that according to the silicidization of the SOI silicon layer subsequent to the formation of a high melting-point metal, a Schottky junction is formed only at each end of the activation region and a PN junction is formed at a portion other than each end thereof.

Abstract: A device isolation region made up of a silicon oxide film, which is perfectly isolated up to the direction of the thickness of an SOI silicon layer, and an activation region of the SOI silicon layer, whose only ends are locally thinned, are formed on an SOI substrate. A source diffusion layer and a drain diffusion layer of a MOS field effect transistor in the activation region are provided so that according to the silicidization of the SOI silicon layer subsequent to the formation of a high melting-point metal, a Schottky junction is formed only at each end of the activation region and a PN junction is formed at a portion other than each end thereof.

Abstract: A heat treatment for diffusing impurity ions implanted into a silicon layer is performed at a heat treatment temperature which is less than an aggregation temperature of the silicon layer. A thermal aggregation of the silicon layer can be inhibited, thereby reducing a silicon deficiency of the silicon layer.

Abstract: A semiconductor device includes diffusion layers formed in a SOI layer under a side-wall, a channel formed between the diffusion layers, silicide layers sandwiching the diffusion layers wherein interface junctions between the diffusion layers and the silicide layers are (111) silicon planes.