Patents by Inventor Takashi Ichiryu

Takashi Ichiryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230412153
    Abstract: A gate drive circuit includes: an input terminal; a first circuit path inserted into a line connecting the input terminal and a gate of a power transistor; a second circuit path connected in parallel to the first circuit path; and a third circuit path connected in parallel to the second circuit path. The first circuit path includes a gate resistor (Rgon). The second circuit path includes a first capacitor and a first resistor connected in series. The third circuit path includes a second capacitor and a second resistor connected in series. The second capacitor has a capacitance value greater than a capacitance value of the first capacitor. The second resistor has a resistance value greater than a resistance value of the first resistor. The gate resistor (Rgon) has a resistance value greater than the resistance value of the second resistor.
    Type: Application
    Filed: September 5, 2023
    Publication date: December 21, 2023
    Inventors: Yusuke KINOSHITA, Takashi ICHIRYU, Hidetoshi ISHIDA
  • Publication number: 20230412154
    Abstract: A gate drive circuit includes: an input terminal; a first circuit path inserted into a line connecting the input terminal and a gate of a power transistor; a second circuit path connected in parallel to the first circuit path; and a third circuit path connected in parallel to the second circuit path. The first circuit path includes a gate resistor (Rgon). The second circuit path includes a first capacitor and a first resistor connected in series. The third circuit path includes a second capacitor and a second resistor connected in series. The second capacitor has a capacitance value greater than a capacitance value of the first capacitor. The second resistor has a resistance value greater than a resistance value of the first resistor. The gate resistor (Rgon) has a resistance value greater than the resistance value of the second resistor.
    Type: Application
    Filed: September 5, 2023
    Publication date: December 21, 2023
    Inventors: Yusuke KINOSHITA, Takashi ICHIRYU, Hidetoshi ISHIDA
  • Patent number: 11791803
    Abstract: A gate drive circuit includes: an input terminal; a first circuit path inserted into a line connecting the input terminal and a gate of a power transistor; a second circuit path connected in parallel to the first circuit path; and a third circuit path connected in parallel to the second circuit path. The first circuit path includes a gate resistor (Rgon). The second circuit path includes a first capacitor and a first resistor connected in series. The third circuit path includes a second capacitor and a second resistor connected in series. The second capacitor has a capacitance value greater than a capacitance value of the first capacitor. The second resistor has a resistance value greater than a resistance value of the first resistor. The gate resistor (Rgon) has a resistance value greater than the resistance value of the second resistor.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: October 17, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yusuke Kinoshita, Takashi Ichiryu, Hidetoshi Ishida
  • Patent number: 11637552
    Abstract: A speed-up circuit is configured to be provided between a power supply terminal and a gate of a semiconductor switching element. An impedance element is configured to be provided between a signal input terminal and a node, the node being between the speed-up circuit and the gate of the semiconductor switching element. In the speed-up circuit, a second field effect transistor is connected in series to a first field effect transistor and is configured to be connected to the gate of the semiconductor switching element. The impedance element has an impedance higher than an impedance of the speed-up circuit when both the first field effect transistor and the second field effect transistor are in an ON state.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: April 25, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yusuke Kinoshita, Takashi Ichiryu, Ryusuke Kanomata, Hidetoshi Ishida
  • Publication number: 20220310835
    Abstract: A bidirectional switch module includes a plurality of bidirectional switches and a mount board. Each of the plurality of bidirectional switches includes a first source electrode, a first gate electrode, a second gate electrode, and a second source electrode. On the mount board, the plurality of bidirectional switches are mounted. In the bidirectional switch module, the plurality of bidirectional switches are connected in parallel.
    Type: Application
    Filed: May 14, 2020
    Publication date: September 29, 2022
    Inventors: Takashi ICHIRYU, Yusuke KINOSHITA, Ryusuke KANOMATA, Masanori NOMURA, Hidetoshi ISHIDA
  • Publication number: 20220271738
    Abstract: A gate drive circuit includes: an input terminal; a first circuit path inserted into a line connecting the input terminal and a gate of a power transistor; a second circuit path connected in parallel to the first circuit path; and a third circuit path connected in parallel to the second circuit path. The first circuit path includes a gate resistor (Rgon). The second circuit path includes a first capacitor and a first resistor connected in series. The third circuit path includes a second capacitor and a second resistor connected in series. The second capacitor has a capacitance value greater than a capacitance value of the first capacitor. The second resistor has a resistance value greater than a resistance value of the first resistor. The gate resistor (Rgon) has a resistance value greater than the resistance value of the second resistor.
    Type: Application
    Filed: July 10, 2020
    Publication date: August 25, 2022
    Inventors: Yusuke KINOSHITA, Takashi ICHIRYU, Hidetoshi ISHIDA
  • Publication number: 20220224321
    Abstract: A speed-up circuit is configured to be provided between a power supply terminal and a gate of a semiconductor switching element. An impedance element is configured to be provided between a signal input terminal and a node, the node being between the speed-up circuit and the gate of the semiconductor switching element. In the speed-up circuit, a second field effect transistor is connected in series to a first field effect transistor and is configured to be connected to the gate of the semiconductor switching element. The impedance element has an impedance higher than an impedance of the speed-up circuit when both the first field effect transistor and the second field effect transistor are in an ON state.
    Type: Application
    Filed: April 28, 2020
    Publication date: July 14, 2022
    Inventors: Yusuke KINOSHITA, Takashi ICHIRYU, Ryusuke KANOMATA, Hidetoshi ISHIDA
  • Patent number: 11257733
    Abstract: A semiconductor device includes a supporting substrate, a semiconductor chip, a resin member, and a heat-dissipating metal layer. The supporting substrate has a first surface and a second surface located opposite from each other in a thickness direction defined for the supporting substrate. The semiconductor chip includes a plurality of electrodes. The semiconductor chip is bonded to the supporting substrate on one side thereof with the first surface. The resin member has a first surface and a second surface located opposite from each other in a thickness direction defined for the resin member. The resin member covers at least a side surface of the supporting substrate and a side surface of the semiconductor chip. The heat-dissipating metal layer is arranged in contact with the supporting substrate and the resin member to cover the second surface of the supporting substrate and the second surface of the resin member at least partially.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: February 22, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takashi Ichiryu, Masanori Nomura, Yusuke Kinoshita, Hidetoshi Ishida, Yasuhiro Yamada
  • Publication number: 20210408934
    Abstract: A GaN layer is formed over the substrate. An AlGaN layer is formed on the GaN layer. A first source electrode, a first gate electrode, a second gate electrode, and a second source electrode are formed on or over the AlGaN layer. A first p-type Alx1Ga1-x1N layer where 0?x1<1 is interposed between the first gate electrode and the AlGaN layer. A second p-type Alx2Ga1-x2N layer where 0?x2<1 is interposed between the second gate electrode and the AlGaN layer. The substrate is electrically insulated from all of the first source electrode, the second source electrode, the first gate electrode, and the second gate electrode. The bidirectional switch further includes a terminal used to connect the substrate to a fixed potential node. The terminal is connected to the substrate.
    Type: Application
    Filed: August 23, 2019
    Publication date: December 30, 2021
    Inventors: Yusuke KINOSHITA, Yasuhiro YAMADA, Takashi ICHIRYU, Masanori NOMURA, Hidetoshi ISHIDA
  • Patent number: 11062981
    Abstract: A bidirectional switch includes: a first lateral transistor including a first semiconductor layer on the surface of a first conductive layer; a second lateral transistor including a second semiconductor layer on the surface of a second conductive layer; a connection member; a first conductor member; and a second conductor member. The connection member connects the first lateral transistor and the second lateral transistor together in anti-series. The first conductor member electrically connects the first source electrode of the first lateral transistor to the first conductive layer. The second conductor member electrically connects the second source electrode of the second lateral transistor to the second conductive layer.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: July 13, 2021
    Assignee: Panasonic Corporation
    Inventors: Yusuke Kinoshita, Yasuhiro Yamada, Takashi Ichiryu, Hidekazu Umeda
  • Publication number: 20210104453
    Abstract: A bidirectional switch includes: a first lateral transistor including a first semiconductor layer on the surface of a first conductive layer; a second lateral transistor including a second semiconductor layer on the surface of a second conductive layer; a connection member; a first conductor member; and a second conductor member. The connection member connects the first lateral transistor and the second lateral transistor together in anti-series. The first conductor member electrically connects the first source electrode of the first lateral transistor to the first conductive layer. The second conductor member electrically connects the second source electrode of the second lateral transistor to the second conductive layer.
    Type: Application
    Filed: March 26, 2018
    Publication date: April 8, 2021
    Inventors: Yusuke KINOSHITA, Yasuhiro YAMADA, Takashi ICHIRYU, Hidekazu UMEDA
  • Publication number: 20200027814
    Abstract: A semiconductor device includes a supporting substrate, a semiconductor chip, a resin member, and a heat-dissipating metal layer. The supporting substrate has a first surface and a second surface located opposite from each other in a thickness direction defined for the supporting substrate. The semiconductor chip includes a plurality of electrodes. The semiconductor chip is bonded to the supporting substrate on one side thereof with the first surface. The resin member has a first surface and a second surface located opposite from each other in a thickness direction defined for the resin member. The resin member covers at least a side surface of the supporting substrate and a side surface of the semiconductor chip. The heat-dissipating metal layer is arranged in contact with the supporting substrate and the resin member to cover the second surface of the supporting substrate and the second surface of the resin member at least partially.
    Type: Application
    Filed: March 27, 2018
    Publication date: January 23, 2020
    Inventors: Takashi ICHIRYU, Masanori NOMURA, Yusuke KINOSHITA, Hidetoshi ISHIDA, Yasuhiro YAMADA
  • Patent number: 10228806
    Abstract: A flexible touch sensor comprises: a first sheet material that has a first major surface, and that has a cushioning property; a second sheet material that includes a conductive material, and that is disposed on the first major surface of the first sheet material; and a conductive wire that is disposed on the first major surface of the first sheet material, and that is sunk into the first sheet material.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: March 12, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Yoshihiro Tomita, Koji Kawakita, Koichi Hirano, Masanori Nomura, Susumu Sawada, Takashi Ichiryu
  • Patent number: 10083889
    Abstract: An electronic component package includes: a sealing resin layer; a metal member buried therein and including a die bond portion and a terminal electrode portion located outside the die bond portion; a ceramic substrate buried in the sealing resin layer; and an electronic component disposed on the die bond portion. When viewed in plan, the die bond portion and the ceramic substrate are partially overlapped to be in contact with each other, and the terminal electrode portion and the ceramic substrate are partially overlapped to be in contact with each other. The electronic component is electrically connected to the terminal electrode portion. The metal member includes a first plating layer and a second plating layer, and the average crystal grain diameter of the first plating layer is smaller than the average crystal grain diameter of the second plating layer.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: September 25, 2018
    Assignee: PANASONIC CORPORATION
    Inventors: Takashi Ichiryu, Koji Kawakita, Masanori Nomura
  • Patent number: 9860979
    Abstract: A stretchable flexible substrate according to one aspect of the present disclosure includes: an electronic component; a first insulating layer located around the electronic component and having first and second main surfaces facing each other; a first metal layer that is in contact with the first main surface; a second metal layer that is in contact with the second main surface and electrically connected to the electronic component; and a second insulating layer that seals the electronic component, first insulating layer, and second metal layer, in plan view, a curved wiring portion extending from a central portion made up of at least the electronic component, portions of the first insulating layer and first and second metal layers, the curved wiring portion being made up of at least other portions of the first insulating layer, first and second metal layers, and the curved wiring portion being curved at least partially.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: January 2, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takashi Ichiryu, Koji Kawakita, Masanori Nomura, Yoshihiro Tomita
  • Patent number: 9844133
    Abstract: A flexible substrate is provided with: a stretchable sheet; a member located on the sheet; and a stretchable strip connected to the member, and located on the sheet. When the amount of extension of the sheet is equal to or less than a predetermined value, the sheet has a first elastic modulus, and when the amount of extension of the sheet exceeds the predetermined value, the sheet has a second elastic modulus that is greater than the first elastic modulus and greater than the elastic modulus of the strip.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: December 12, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yoshihiro Tomita, Koichi Hirano, Susumu Sawada, Koji Kawakita, Takashi Ichiryu, Masanori Nomura
  • Publication number: 20170352603
    Abstract: An electronic component package includes: a sealing resin layer; a metal member buried therein and including a die bond portion and a terminal electrode portion located outside the die bond portion; a ceramic substrate buried in the sealing resin layer; and an electronic component disposed on the die bond portion. When viewed in plan, the die bond portion and the ceramic substrate are partially overlapped to be in contact with each other, and the terminal electrode portion and the ceramic substrate are partially overlapped to be in contact with each other. The electronic component is electrically connected to the terminal electrode portion. The metal member includes a first plating layer and a second plating layer, and the average crystal grain diameter of the first plating layer is smaller than the average crystal grain diameter of the second plating layer.
    Type: Application
    Filed: May 16, 2017
    Publication date: December 7, 2017
    Inventors: TAKASHI ICHIRYU, KOJI KAWAKITA, MASANORI NOMURA
  • Patent number: 9812385
    Abstract: An electronic component package according to one aspect of the present disclosure includes a metal pattern layer having a first principal surface and a second principal surface, an electronic component disposed on the first principal surface and electrically connected to the metal pattern layer, at least one metal member disposed on the first principal surface and electrically connected to the metal pattern layer, a sealing resin layer disposed on the first principal surface, the electronic component and the at least one metal member, and an insulating layer disposed on the second principal surface. The at least one metal member is thicker than the electronic component. In plan view, the at least one metal member is disposed on an area of the first principal surface, the area including an end of the first principal surface. The at least a part of the metal pattern layer is exposed from the insulating layer.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: November 7, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Koji Kawakita, Takashi Ichiryu, Masanori Nomura
  • Publication number: 20170300147
    Abstract: A flexible touch sensor comprises: a first sheet material that has a first major surface, and that has a cushioning property; a second sheet material that includes a conductive material, and that is disposed on the first major surface of the first sheet material; and a conductive wire that is disposed on the first major surface of the first sheet material, and that is sunk into the first sheet material.
    Type: Application
    Filed: April 7, 2017
    Publication date: October 19, 2017
    Inventors: Yoshihiro TOMITA, Koji KAWAKITA, Koichi HIRANO, Masanori NOMURA, Susumu SAWADA, Takashi ICHIRYU
  • Publication number: 20170181277
    Abstract: A flexible substrate is provided with: a stretchable sheet; a member located on the sheet; and a stretchable strip connected to the member, and located on the sheet. When the amount of extension of the sheet is equal to or less than a predetermined value, the sheet has a first elastic modulus, and when the amount of extension of the sheet exceeds the predetermined value, the sheet has a second elastic modulus that is greater than the first elastic modulus and greater than the elastic modulus of the strip.
    Type: Application
    Filed: November 29, 2016
    Publication date: June 22, 2017
    Inventors: YOSHIHIRO TOMITA, KOICHI HIRANO, SUSUMU SAWADA, KOJI KAWAKITA, TAKASHI ICHIRYU, MASANORI NOMURA