Patents by Inventor Takashi Inagawa
Takashi Inagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7208113Abstract: To provide a method of producing an encapsulating molding material tablet by which adhesion of an encapsulating molding material to the punch surface of a tablet forming machine can be reduced, an encapsulating molding material tablet produced by this method, and an electronic part apparatus equipped with an element encapsulated using this encapsulating molding material tablet. A method of producing an encapsulating molding material tablet in which a release agent dissolved in a solvent is fed to the punch surface of a tablet forming machine to form a release agent layer having a thickness of over 0.001 ?m and less than 0.07 ?m on the above-mentioned punch surface, then, an encapsulating molding material is fed to the above-mentioned tablet forming machine for molding the material, an encapsulating molding material tablet produced by this method or having a contact angle ratio of 1.15 or more and less than 1.Type: GrantFiled: October 24, 2002Date of Patent: April 24, 2007Assignee: Hitachi Chemical Co., Ltd.Inventors: Katsumi Kubo, Takashi Inagawa, Hiroshi Terada, Akio Ono, Hiroshi Masubuchi, Tateo Yamada
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Patent number: 7000153Abstract: A computer apparatus and a method of diagnosing are provided that increase reliability and make non-stop operation possible even at a hardware repair, replacement, or addition time. The computer apparatus, which comprises a main OS and a sub OS, may have a peripheral device or an I/O card repaired, replaced, or added with power on. The repaired, replaced, or added hardware component is disconnected from the main OS. With the main OS performing usual processing, the sub OS uses a test/maintenance program to check the operation of the repaired, replaced, or added hardware component and then passes the control of the hardware component to the main OS.Type: GrantFiled: June 4, 2002Date of Patent: February 14, 2006Assignee: Hitachi, Ltd.Inventors: Takashi Inagawa, Yasuo Hirata, Teiji Karasaki, Shinji Kimura
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Publication number: 20050040561Abstract: To provide a method of producing an encapsulating molding material tablet by which adhesion of an encapsulating molding material to the punch surface of a tablet forming machine can be reduced, an encapsulating molding material tablet produced by this method, and an electronic part apparatus equipped with an element encapsulated using this encapsulating molding material tablet. A method of producing an encapsulating molding material tablet in which a release agent dissolved in a solvent is fed to the punch surface of a tablet forming machine to form a release agent layer having a thickness of over 0.001 ?m and less than 0.07 ?m on the above-mentioned punch surface, then, an encapsulating molding material is fed to the above-mentioned tablet forming machine for molding the material, an encapsulating molding material tablet produced by this method or having a contact angle ratio of 1.15 or more and less than 1.Type: ApplicationFiled: October 24, 2002Publication date: February 24, 2005Applicant: HITACHI CHEMICAL CO., LTDInventors: Katsumi Kubo, Takashi Inagawa, Hiroshi Terada, Akio Ono, Hiroshi Masubuchi, Tateo Yamada
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Publication number: 20020184563Abstract: A computer apparatus and a method of diagnosing are provided that increase reliability and make non-stop operation possible even at a hardware repair, replacement, or addition time. The computer apparatus, which comprises a main OS and a sub OS, may have a peripheral device or an I/O card repaired, replaced, or added with power on. The repaired, replaced, or added hardware component is disconnected from the main OS. With the main OS performing usual processing, the sub OS uses a test/maintenance program to check the operation of the repaired, replaced, or added hardware component and then passes the control of the hardware component to the main OS.Type: ApplicationFiled: June 4, 2002Publication date: December 5, 2002Inventors: Takashi Inagawa, Yasuo Hirata, Teiji Karasaki, Shinji Kimura
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Patent number: 6378028Abstract: A bus switching structure and a computer using the same, wherein input/output (I/O) slot connections are switched to a desired I/O bus so that loads are distributed evenly over the I/O buses. The bus switching structure includes a switching unit and switching controller. The switching unit is located interposingly between an I/O slot and a plurality of I/O buses. The switching unit either connects or disconnects the I/O slot to or from each of the I/O buses in accordance with a switching signal. The switching controller outputs the switching signal to cause the switching unit to connect the I/O slot to one of the I/O buses and to disconnect the I/O slot from any of the other I/O bus, thereby effecting connection switchover between the I/O slot and the I/O buses.Type: GrantFiled: May 7, 2001Date of Patent: April 23, 2002Assignee: Hitachi, Ltd.Inventors: Takashi Inagawa, Yoshiaki Hisada, Junya Ide
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Publication number: 20010020258Abstract: A bus switching structure and a computer using the same, wherein input/output (I/O) slot connections are switched to a desired I/O bus so that loads are distributed evenly over the I/O buses. The bus switching structure includes a switching unit and switching controller. The switching unit is located interposingly between an I/O slot and a plurality of I/O buses. The switching unit either connects or disconnects the I/O slot to or from each of the I/O buses in accordance with a switching signal. The switching controller outputs the switching signal to cause the switching unit to connect the I/O slot to one of the I/O buses and to disconnect the I/O slot from any of the other I/O bus, thereby effecting connection switchover between the I/O slot and the I/O buses.Type: ApplicationFiled: May 7, 2001Publication date: September 6, 2001Inventors: Takashi Inagawa, Yoshiaki Hisada, Junya Ide
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Patent number: 6263394Abstract: A bus switching structure and a computer using the same, wherein input/output (I/O) slot connections are switched to a desired I/O bus so that loads are distributed evenly over the I/O buses. The bus switching structure includes a switching unit and switching controller. The switching unit is located interposingly between an I/O slot and a plurality of I/O buses. The switching unit either connects or disconnects the I/O slot to or from each of the I/O buses in accordance with a switching signal. The switching controller outputs the switching signal to cause the switching unit to connect the I/O slot to one of the I/O buses and to disconnect the I/O slot from any of the other I/O bus, thereby effecting connection switchover between the I/O slot and the I/O buses.Type: GrantFiled: March 13, 2000Date of Patent: July 17, 2001Assignee: Hitachi, LTDInventors: Takashi Inagawa, Yoshiaki Hisada, Junya Ide
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Patent number: 6073202Abstract: A bus switching structure and a computer using the same, wherein input/output (I/O) slot connections are switched to a desired I/O bus so that loads are distributed evenly over the I/O buses. The bus switching structure includes a switching unit and switching controller. The switching unit is located interposingly between an I/O slot and a plurality of I/O buses. The switching unit either connects or disconnects the I/O slot to or from each of the I/O buses in accordance with a switching signal. The switching controller outputs the switching signal to cause the switching unit to connect the I/O slot to one of the I/O buses and to disconnect the I/O slot from any of the other I/O bus, thereby effecting connection switchover between the I/O slot and the I/O buses.Type: GrantFiled: August 18, 1998Date of Patent: June 6, 2000Assignee: Hitachi, Ltd.Inventors: Takashi Inagawa, Yoshiaki Hisada, Junya Ide
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Patent number: 5572701Abstract: Bus snoop method and apparatus for use in a computer system in which a CPU with cache is coupled to a main memory control unit for controlling a main memory unit through a bus snoop control unit, wherein when the CPU with cache occupies a bus at the time that an external bus master transfers data to the main memory unit, a transfer address for transfer of the data undergoes buffering in the bus snoop control unit and after the CPU with cache ends the execution of an instruction and opens a bus right, the bus snoop control unit transfers the data transfer address subject to buffering to the CPU with cache and a corresponding address recorded in the cache is canceled.Type: GrantFiled: April 19, 1994Date of Patent: November 5, 1996Assignees: Hitachi, Ltd., Hitachi Chubu Software, Ltd.Inventors: Kazuhisa Ishida, Takashi Inagawa, Katuya Banno
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Patent number: 5557760Abstract: A processor for use in a data processing system with a cache RAM and main memory has a control pin for deactivating the driving of the data bus without deactivating that of the address bus during a write cycle. This capability is useful during a cache storing operation following a miss for performing a write operation without the requirement of additional address storing circuitry. In particular, during a cache storing operation, the processor can drive the address bus while control of the data bus by the processor is floated. Then, the data in main memory can be put on the data bus and transferred into the cache memory. Once the data is transferred to the cache memory, the original write operation can be completed.Type: GrantFiled: September 8, 1993Date of Patent: September 17, 1996Assignee: Hitachi, Ltd.Inventors: Osamu Nishii, Takashi Inagawa, Makoto Hanawa, Hiroshi Takeda
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Patent number: 4290037Abstract: A flat electromagnetic relay which includes a base member having at least two projections extending from a flat surface thereof. At least one hole (or indent), fitting a pertinent one of the projections, is formed in each supporting block that holds a contact, yoke, a hinging spring, or the like. These and similar members are successively stacked on the surface of the base member, with the projections fitted through the holes in the supporting blocks. The free ends of the respective projections are then deformed to secure and hold the components in position. A contact actuating card is put in place after the stack of contact holding blocks is assembled and locked in position. The block through which a contact carrying leaf spring is molded preferably has an end surface formed at an angle such that a portion of the leaf spring may be subsequently bent to extend substantially perpendicular to the remainder of the leaf spring, thereby forming a solder terminal.Type: GrantFiled: February 21, 1979Date of Patent: September 15, 1981Assignee: Nippon Electric Co., Ltd.Inventors: Takashi Inagawa, Naoto Kushida, Akira Sekiguchi, Matujiro Ikeda, Hidetoshi Sugawara, Kunio Naito
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Patent number: 4060782Abstract: A switching device is provided which is of a highly integrated structure and particularly adapted for a matrix arrangement of switch elements. The structure characteristically enables the switching device to be efficiently fabricated with maximum component density and minimum cost, and includes a base plate in the form of an integral combination of two insulating plates lying on each other, fixed contacts formed in an appropriate pattern on one of the insulating plates, and movable contacts formed integrally with spring strips supported on the base plate.Type: GrantFiled: February 19, 1976Date of Patent: November 29, 1977Assignee: Nippon Electric Company, LimitedInventors: Takashi Inagawa, Sadayuki Mitsuhashi