Patents by Inventor Takashi Inamasu

Takashi Inamasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7030313
    Abstract: A thin film solar cell comprises a p-layer, an i-layer and an n-layer formed in this order as a pin junction on a substrate in which the p-layer and the i-layer are thin silicon films each containing a crystalline component, and the p-layer contains p-type impurities of 0.2 to 8 atom % and has a thickness of 10 to 200 nm.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: April 18, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takashi Inamasu, Masafumi Shimizu, Kenji Wada
  • Publication number: 20030127127
    Abstract: A thin film solar cell comprises a p-layer, an i-layer and an n-layer formed in this order as a pin junction on a substrate in which the p-layer and the i-layer are thin silicon films each containing a crystalline component, and the p-layer contains p-type impurities of 0.2 to 8 atom % and has a thickness of 10 to 200 nm.
    Type: Application
    Filed: November 22, 2002
    Publication date: July 10, 2003
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Takashi Inamasu, Masafumi Shimizu, Kenji Wada
  • Patent number: 6512171
    Abstract: A thin film solar cell comprises a p-layer, an i-layer and an n-layer formed in this order as a pin junction on a substrate in which the p-layer and the i-layer are thin silicon films each containing a crystalline component, and the p-layer contains p-type impurities of 0.2 to 8 atom % and has a thickness of 10 to 200 nm.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: January 28, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takashi Inamasu, Masafumi Shimizu, Kenji Wada
  • Publication number: 20010035206
    Abstract: A thin film solar cell comprises a p-layer, an i-layer and an n-layer formed in this order as a pin junction on a substrate in which the p-layer and the i-layer are thin silicon films each containing a crystalline component, and the p-layer contains p-type impurities of 0.2 to 8 atom % and has a thickness of 10 to 200 nm.
    Type: Application
    Filed: January 12, 2001
    Publication date: November 1, 2001
    Inventors: Takashi Inamasu, Masafumi Shimizu, Kenji Wada