Abstract: An information processing system which has (a) a CPU that is operated in a normal mode during which the CPU is driven at a relatively fast operating clock rate, and a power saving mode during which the operating clock has a lower rate or is halted; (b) at least one peripheral device; (c) a bus for performing communication between the CPU and the peripheral device; (d) a termination detector detecting a completion of a predetermined transaction between the CPU and the peripheral device; (e) a time counter measuring a predetermined period of time after the completion of the predetermined transaction; and (f) a power saving control causing the CPU enter the power saving mode until the time counted by the time counting means reaches the predetermined period of time.

Abstract: A device for printing on a continuous sheet includes a motor for carrying the continuous sheet, a switching unit for switching a minimum unit of control of the motor depending on a paper size of the continuous sheet, and a position-detection unit for detecting a rotational position of the motor. The device further includes a stop-control unit for controlling the motor to stop at a position matching a selected minimum unit of control based on the rotational position of the motor detected by the position-detection unit.

Abstract: An information processing system and method is disclosed that can automatically establish a software environment suitable for a hardware configuration without the operator's intervention even if the hardware configuration for the information processing system changes. This is accomplished by establishing a file of system configurations describing the data for any previously established software system environment. The file is stored in the information processing system and is changed based on any hardware changes so that the software system configuration can also change.

Abstract: An input circuit for a memory address bit operates at high operating speed. A PMOS transistor 112 is provided between a supply line for 1/2V.sub.CC and a node N11. When not in operation, node N11 of input portion 11A is precharged not to the power supply voltage V.sub.CC, but to 1/2V.sub.CC, a potential halfway between the power supply voltage V.sub.CC and 0 V. Another PMOS transistor 117 is provided between a PMOS transistor 111 and node N11 of the input stage to prevent leakage between V.sub.CC and 1/2V.sub.CC. As a result, an enable signal ENB goes to a high level, the circuit enters the operating state, address bit signal Ai is input, and the time needed to shift the level of node N11 to V.sub.CC or 0 V becomes short.

Abstract: A semiconductor memory device having reserve bit lines or word lines for replacing defective bit lines or word lines which can increase a defect relief probability and improve an operational margin. The reserve bit lines or word lines are provided approximately in a central portion of a memory mat. Because of a low probability of defect occurrence in the reserve word lines or bit lines, the probability of defect occurrence can be made low when a defective word line or bit line is replaced with a reserve word line or bit line.

Abstract: A semiconductor memory device characterized by the fact that the disturb test time of the semiconductor memory device can be shortened, and the power consumption can be cut.In the disturb test for the semiconductor memory device in this invention, multiple word lines are selected at the same time with a prescribed interval corresponding to the element isolation layout. As the word lines are selected corresponding to the element isolating layout, the interference caused by the element isolation state can be excluded. Since multiple word lines are selected at the same time, the time of operation can be shortened. Since the word lines are maintained in the selected state while the sense amplifiers are not reset, there is no increase in the power consumption although multiple word lines are selected at the same time.

Abstract: A word line driving circuit which effectively prevents ground noise during word line discharge along with accommodating the narrowing of pitch in the word lines by making the layout area of the word line driver small. The word line driving circuit includes n-type MOS transistor 14 and p-type MOS transistor 12. The drain terminal of n-type MOS transistor 14 and drain terminal of p-type MOS transistor 12 in word line driver 10 are connected to the base terminal of word line WLi. The output terminal of an output transistor driving circuit 16 is connected to the source terminal of p-type MOS transistor 12, and the output terminal of a first output transistor controlling circuit 18 is connected to the gate terminal. The output terminal of a second output transistor controlling circuit 20 is connected to the gate terminal of n-type MOS transistor 14, and a ground terminal 22 as a reference potential terminal for leading in the electric current is connected to the source terminal.

Abstract: A dynamic random access memory device has a memory cell array which includes a first memory cell array part and a second memory cell array part portioned in a first direction parallel with the bit lines, a plurality of column switches, one provided for each of the bit lines, a plurality of input/output lines each connected to different ones of the bit lines via associated ones of the column switches, a row address decoder for decoding a first portion of an address signal and a column address decoder for decoding a second portion of the address signal to thereby simultaneously access at least two memory cells with the address signal. The input/output lines extend in a second direction parallel with word lines and are divided into first and second groups of input/output lines connected to those bit lines which belong to the first and second memory cell array parts, respectively in which the first input/output line group is isolated from the second input/output line group.

Abstract: A semiconductor memory device characterized by the fact that the disturb test time of the semiconductor memory/device can be shortened, and the power consumption can be cut.In the disturb test for the semiconductor memory device in this invention, multiple word lines are selected at the same time with a prescribed interval corresponding to the element isolation layout. As the word lines are selected corresponding to the element isolating layout, the interference caused by the element isolation state can be excluded. Since multiple word lines are selected at the same time, the time of operation can be shortened. Since the word lines are maintained in the selected state while the sense amplifiers are not reset, there is no increase in the power consumption although multiple word lines are selected at the same time.

Abstract: A driving circuit for providing a predetermined voltage as a driving signal to a respective word line in a dynamic random access memory in a short time. The driving circuit includes an operation signal supply circuit portion for providing an operation signal, a driving signal output circuit portion which receives the operation signal and provides a driving signal as an output, and a voltage supply circuit portion for providing a predetermined voltage to the driving signal output circuit portion in producing the driving signal. A bipolar switching element is provided in the driving signal output circuit portion to control the voltage supply from the voltage supply circuit portion and responds to the operation signal to provide the voltage from the voltage supply circuit portion as the voltage producing the driving signal in a short time.

Abstract: Data selector circuit including a plurality of data registers connected in parallel via corresponding output buffers to a plurality of output drivers, wherein a decoder and selector portion is interposed between the output buffers and the output drivers for selectively providing one of a plurality of serial data output sequences from the data registers to the output drivers rather than a parallel data output format from the plurality of data registers which would otherwise occur. The decoder and selector portion is controlled by a partial address buffer which is provided with serial sequence selection data.

Abstract: This invention relates to a semiconductor integrated circuit device which has an insulated-gate type element part comprising a capacitor which is formed through the use of a trench in a semiconductor layer, wherein a low-resistance buried layer is formed in the semiconductor layer prior to forming the trench so that the trench is formed to be surrounded by the low-resistance buried layer and thereby the low-resistance buried layer is used as an electrode of the capacitor.

Abstract: A sense amplifier circuit is described for switching plural inputs at high speed. At least two transistors for providing at least two true input signals are connected in parallel and have their source terminals connected to a common node from which an output signal may be read. Similarly, at least two other transistors for providing the inverse of the true input signals are connected in parallel and their source terminals are connected to another common node from which an inverse of the output signal may be read. The common nodes are then precharged to the same voltage. True and inverse input signals are applied to their respective transistors through transfer gates where all the true input signals are greater than their respective inverse signals. Therefore, the on-resistance of each of the transistors to which a true input is applied have a higher on-resistance than the associated transistors to which an inverse input is applied.