Patents by Inventor Takashi Ippooshi

Takashi Ippooshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device having input-output protection circuit
    Patent number: 6274908
    Abstract: A semiconductor device having a SOI structure in which an ESD resistance can be enhanced is obtained. The semiconductor device comprises PMOS transistors Q21 and Q22 which are brought into a forward bias state if a positive high voltage is applied as a surge voltage to a signal terminal 30, and NMOS transistors Q11 and Q12 which are brought into the forward bias state if a negative high voltage is applied as the surge voltage to the signal terminal 30. Furthermore, if a normal operation signal is applied from the signal terminal 30, all the NMOS transistors Q11 and Q12 and the PMOS transistors Q21 and Q22 are brought into an OFF state.
    Type: Grant
    Filed: April 8, 1998
    Date of Patent: August 14, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Yamaguchi, Takashi Ippooshi