Patents by Inventor Takashi Ishimoto
Takashi Ishimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240161985Abstract: An electrolytic capacitor includes an anode body, a dielectric layer that covers the anode body, a first solid electrolyte layer that covers the dielectric layer, and a second solid electrolyte layer that covers the first solid electrolyte layer. The first solid electrolyte layer contains a first conductive polymer that includes polypyrrole as a basic skeleton. The second solid electrolyte layer contains a second conductive polymer that includes polythiophene as a basic skeleton. The second solid electrolyte layer has a thickness of 1 ?m or more.Type: ApplicationFiled: March 4, 2022Publication date: May 16, 2024Inventors: Shinji KONDOU, Kazuya YAMASAKI, Takashi KAWASAKI, Koji YOKOYAMA, Hitoshi ISHIMOTO, Yoshihisa NAGASAKI, Yuji MIYACHI
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Patent number: 9869715Abstract: The present invention provides a semiconductor wafer inspection apparatus and a semiconductor wafer inspection method that can suppress warpage in a semiconductor wafer due to a temperature difference between the mounting surface of a table and the semiconductor wafer. In a prober of the present invention, a semiconductor wafer is heated to have a second temperature which is equal to or lower than a first temperature in a preheating step using an oven, and then the semiconductor wafer is placed on a mounting surface of a table which is heated to the first temperature. Thus, because a temperature difference between the mounting surface of the table and the semiconductor wafer is reduced in the prober, it is possible to suppress warpage in the semiconductor wafer that occurs right after the semiconductor wafer is placed on the mounting surface.Type: GrantFiled: August 12, 2016Date of Patent: January 16, 2018Assignee: TOKYO SEIMITSU CO., LTD.Inventors: Takashi Ishimoto, Yuji Shigesawa, Akira Yamaguchi, Takashi Motoyama, Takenori Takahashi
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Publication number: 20170010323Abstract: The present invention provides a semiconductor wafer inspection apparatus and a semiconductor wafer inspection method that can suppress warpage in a semiconductor wafer due to a temperature difference between the mounting surface of a table and the semiconductor wafer. In a prober of the present invention, a semiconductor wafer is heated to have a second temperature which is equal to or lower than a first temperature in a preheating step using an oven, and then the semiconductor wafer is placed on a mounting surface of a table which is heated to the first temperature. Thus, because a temperature difference between the mounting surface of the table and the semiconductor wafer is reduced in the prober, it is possible to suppress warpage in the semiconductor wafer that occurs right after the semiconductor wafer is placed on the mounting surface.Type: ApplicationFiled: August 12, 2016Publication date: January 12, 2017Inventors: Takashi ISHIMOTO, Yuji SHIGESAWA, Akira YAMAGUCHI, Takashi MOTOYAMA, Takenori TAKAHASHI
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Publication number: 20100068669Abstract: The present invention provides a continuous heat treatment furnace including: a heating chamber heating a treatment object in an inert gas atmosphere; a front chamber provided at one end of the heating chamber; and a first cooling chamber cooling the treatment object in an inert gas atmosphere, a vacuum purge chamber, and a second cooling chamber cooling the treatment object in an oxidizing gas atmosphere, which are connected in this order to the other end of the heating chamber, in which the treatment object transferred from the front chamber to the heating chamber is subjected to the heating in the heating chamber, and then subjected to one cooling selected from the cooling in the inert gas atmosphere in the first cooling chamber and the cooling in the oxidizing gas atmosphere in the second cooling chamber depending on a type of the treatment object.Type: ApplicationFiled: September 15, 2009Publication date: March 18, 2010Applicant: DAIDO TOKUSHUKO KABUSHIKI KAISHAInventors: Takashi ISHIMOTO, Takaya Ochiai, Kenji Shimizu, Masato Ogawa
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Patent number: 7129507Abstract: The invention is a method for detecting float or peel of semiconductor chips arranged in X and Y axes directions diced and bonded to a dicing tape on a stage. The method includes detecting float or peel of the semiconductor chips in a respective horizontal or longitudinal row arranged in the X or Y axis direction; moving the stage in the X axis direction, the Y axis direction, a Z axis direction, and a rotational direction around the Z axis for aligning the stage with a position detection unit for detecting positions of the semiconductor chips in the X axis direction and the Y axis direction; detecting the positions of abnormal semiconductor chips in the respective horizontal or longitudinal row that includes said abnormal semiconductor chips; and specifying the positions of said abnormal semiconductor chips on the X-Y axes.Type: GrantFiled: February 4, 2005Date of Patent: October 31, 2006Assignee: Tokyo Seimitsu Co., LtdInventors: Akira Yamamoto, Konosuke Murakami, Yoshio Niki, Takashi Ishimoto, Yutaka Ueda
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Publication number: 20050173702Abstract: The invention includes first detection means (9A) disposed on the side of a stage (2), for detecting float or peel of semiconductor chips (10) inside a horizontal or longitudinal row unit regularly arranged in an X or Y axis direction, and second detection means (9B) disposed above the stage (2), for detecting the positions of the semiconductor chips in a unit horizontal or longitudinal row including the peeling semiconductor chips detected by the first detection means, and specifies the positions of the peeling semiconductor chips on the X-Y coordinate axes among a large number of semiconductor chips regularly arranged in the X and Y axes directions by using the first and second detection means while the stage is being moved in the X and Y axes directions.Type: ApplicationFiled: February 4, 2005Publication date: August 11, 2005Inventors: Akira Yamamoto, Konosuke Murakami, Yoshio Niki, Takashi Ishimoto, Yutaka Ueda
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Patent number: 6366102Abstract: An inspection tray on which an inspection wafer is placed is detachably mounted on a special tray on which a cleaning wafer is placed. The special tray can be horizontally drawn out from a body of a wafer probing machine. Thus, it is possible to easily confirm types of cleaning wafer and inspection wafer.Type: GrantFiled: May 12, 1998Date of Patent: April 2, 2002Assignee: Tokyo Seimitsu Co., Ltd.Inventor: Takashi Ishimoto
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Patent number: 5568056Abstract: A test head is rotatably supported by a main body of device. This test head is rotatable between an inspecting position electrically connected to a probe card and a retracted position being retracted from the inspecting position. The test head is connected thereto with a cylinder for weight balance for decreasing the tare of the test head, and the center of rotation of the connecting point of the cylinder for weight balance is made eccentric from the center of rotation of the test head. With this arrangement, the balancing force of the cylinder for weight balance can be rendered to the test head without fluctuations. As described above, the balancing force can be rendered to the test head during the rotation of the test head without fluctuations, so that the rotating operation of the test head can be facilitated.Type: GrantFiled: November 25, 1994Date of Patent: October 22, 1996Assignee: Tokyo Seimitsu Co., Ltd.Inventor: Takashi Ishimoto
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Patent number: 5002009Abstract: A furnace for the formation of a black oxide film on the surface of a thin metal sheet is disclosed which comprises a tunnel-like furnace proper provided at one terminal side thereof with an inlet and at the other terminal side thereof with an outlet, conveying means laid inside the furnace proper from the inlet through the outlet thereof for conveying a thin metal sheet from the inlet to the outlet, openable shutter means for partitioning the interior of the furnace proper into at least first and second regions on the front and rear sides respectively in the direction of conveyance of the thin metal sheet, first gas supply means for feeding into the first region on the inlet side of the furnace proper partitioned by the shutter means a mixed gas containing carbon dioxide and carbon monoxide and containing substantially no oxygen or a mixed gas containing carbon dioxide, carbon monoxide, and steam and containing substantially no oxygen, second gas supply means for feeding into the second region on the outletType: GrantFiled: July 13, 1989Date of Patent: March 26, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Toshitomo Hayami, Humio Shibata, Katsumi Iguchi, Hisao Inoue, Takashi Ono, Takashi Ishimoto
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Patent number: 4859251Abstract: A furnace for the formation of a black oxide film on the surface of a thin metal sheet is disclosed which comprises a tunnel-like furnace proper provided at one terminal side thereof with an inlet and at the other terminal side thereof with an outlet, conveying means laid inside the furnace proper from the inlet through the outlet thereof for conveying a thin metal sheet from the inlet to the outlet, openable shutter means for partitioning the interior of the furnace proper into at least first and second regions on the front and rear sides respectively in the direction of conveyance of the thin metal sheet, first gas supply means for feeding into the first region on the inlet side of the furnace proper partitioned by the shutter means a mixed gas containing carbon dioxide and carbon monoxide and containing substantially no oxygen or a mixed gas containing carbon dioxide, carbon monoxide, and steam and containing substantially no oxygen, second gas supply means for feeding into the second region on the outletType: GrantFiled: March 4, 1988Date of Patent: August 22, 1989Assignee: Kabushiki Kaisha ToshibaInventors: Toshitomo Hayami, Humio Shibata, Katsumi Iguchi, Hisao Inoue, Takashi Ono, Takashi Ishimoto