Abstract: The present disclosure makes it possible to perform a failure diagnosis of an electric two-wheeled vehicle easily, conveniently, and immediately. The electric two-wheeled vehicle includes an electric equipment unit having an IC tag and a host unit. The host unit is capable of communicating with the IC tag, and obtains failure information of the electric equipment unit while electric power is supplied from the battery to the electric equipment unit. The information communication terminal obtains the failure information by communicating with the electric two-wheeled vehicle in a non-contact manner, and transmits the failure information to the server via the network. The server performs a failure diagnosis on the electric two-wheeled vehicle based on the failure information.

Abstract: The present disclosure makes it possible to perform a failure diagnosis of an electric two-wheeled vehicle easily, conveniently, and immediately. The electric two-wheeled vehicle includes an electric equipment unit having an IC tag and a host unit. The host unit is capable of communicating with the IC tag, and obtains failure information of the electric equipment unit while electric power is supplied from the battery to the electric equipment unit. The information communication terminal obtains the failure information by communicating with the electric two-wheeled vehicle in a non-contact manner, and transmits the failure information to the server via the network. The server performs a failure diagnosis on the electric two-wheeled vehicle based on the failure information.

Abstract: In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power supply to the combinational circuit can be performed separately from, and independently of, each other. During shift operation in scan testing, the power supply voltage to the combinational circuit is set to a low voltage or cut off, thereby suppressing the amount of power consumed by the combinational circuit portion during the shift operation. At the same time, the power supply voltage to the flip flop circuits is set to a high voltage during the shift operation.

Abstract: In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power supply to the combinational circuit can be performed separately from, and independently of, each other. During shift operation in scan testing, the power supply voltage to the combinational circuit is set to a low voltage or cut off, thereby suppressing the amount of power consumed by the combinational circuit portion during the shift operation. At the same time, the power supply voltage to the flip flop circuits is set to a high voltage during the shift operation.

Abstract: In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power supply to the combinational circuit can be performed separately from, and independently of, each other. During shift operation in scan testing, the power supply voltage to the combinational circuit is set to a low voltage or cut off, thereby suppressing the amount of power consumed by the combinational circuit portion during the shift operation. At the same time, the power supply voltage to the flip flop circuits is set to a high voltage during the shift operation.

Abstract: In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power supply to the combinational circuit can be performed separately from, and independently of, each other. During shift operation in scan testing, the power supply voltage to the combinational circuit is set to a low voltage or cut off, thereby suppressing the amount of power consumed by the combinational circuit portion during the shift operation. At the same time, the power supply voltage to the flip flop circuits is set to a high voltage during the shift operation.

Abstract: A semiconductor integrated circuit of the present invention is provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving a clock output command signal from the outside, and an internal circuit controlled by an output clock signal that is output from the clock control portion, and the clock control portion is configured so that it outputs the output clock signal to the internal circuit when a certain time period has passed from a time when the output command signal is received.

Abstract: To provide a semiconductor integrated circuit device in which an occupied area is suppressed from increasing and a high-performance test circuit is included, There is provided a semiconductor integrated circuit having a test circuit, by determining arrangement positions of cells forming a circuit to be tested and non-connected cells prepared to form a test circuit and then determining a connection relationship among the non-connected cells prepared to form the test circuit on the basis of the arrangement information to thereby form the test circuit.

Abstract: A circuit structure analysis unit performs structure analysis for logic circuit information, obtained from an HDL description, and acquires analysis results for function parts, such as a register, an operation unit and a multiplexer. A synthesis instruction generation unit compares the analysis results with a synthesis instruction correlation rule, and automatically generates a synthesis instruction to control a logic synthesis method. Finally, an HDL description output unit outputs a synthesis instruction added HDL description, wherein a synthesis instruction is inserted into the original HDL description. When the synthesis instruction added HDL description is employed in the logic synthesis, starting at the top hierarchical level, a synthesis instruction for the logic circuit is not required in a synthesis execution script.

Abstract: A semiconductor integrated circuit of the present invention is provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving a clock output command signal from the outside, and an internal circuit controlled by an output clock signal that is output from the clock control portion, and the clock control portion is configured so that it outputs the output clock signal to the internal circuit when a certain time period has passed from a time when the output command signal is received.

Abstract: In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power supply to the combinational circuit can be performed separately from, and independently of, each other. During shift operation in scan testing, the power supply voltage to the combinational circuit is set to a low voltage or cut off, thereby suppressing the amount of power consumed by the combinational circuit portion during the shift operation. At the same time, the power supply voltage to the flip flop circuits is set to a high voltage during the shift operation.

Abstract: A semiconductor integrated circuit of the present invention is provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving a clock output command signal from the outside, and an internal circuit controlled by an output clock signal that is output from the clock control portion, and the clock control portion is configured so that it outputs the output clock signal to the internal circuit when a certain time period has passed from a time when the output command signal is received.