Patents by Inventor Takashi Ishinaka

Takashi Ishinaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140297956
    Abstract: An arithmetic processing apparatus includes a plurality of first processing units to be connected to a cache memory; a plurality of second processing units to be connected to the cache memory and to acquire, into the cache memory, data to be processed by the first processing unit before each of the plurality of first processing units executes processing; and a schedule processing unit to control a schedule for acquiring the data of the plurality of second processing units into the cache memory.
    Type: Application
    Filed: March 13, 2014
    Publication date: October 2, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Takashi Ishinaka, Jun Moroo