Patents by Inventor Takashi Ishitobi

Takashi Ishitobi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080054260
    Abstract: A wafer test is performed to a wafer, and then a protective film is applied to part of a chip surface of each good chip other than terminals. For defective chips, a protective film is applied to an entire chip surface as well as terminals and, while keeping that state, a burn-in test is performed, thereby cutting off power supply and signal application to defective chips before burn-in test. Moreover, when a chip includes a self-test circuit to judge whether the chip is good or not and the chip is judged to be defective, the function of stopping an internal operation of the chip may be provided or a judgment signal may be transmitted to a burn-in test apparatus, thereby stopping power supply and signal application from the burn-in test apparatus. Thus, power supply and signal application to a chip judged to be defective after burn-in can be cut off.
    Type: Application
    Filed: June 1, 2005
    Publication date: March 6, 2008
    Inventors: Takashi Ishitobi, Takashi Ohtori, Yasushi Tanaka