Abstract: A test on a desired internal voltage is easily and accurately conducted without increasing current dissipation or the number of pads. A driving circuit receiving a reference voltage from a reference voltage generating circuit has a high input impedance and low output impedance, and generates a voltage substantially at the same voltage level as the reference voltage received, and transmits the generated voltage to a pad with a current driving capability larger than the driving current capability of the reference voltage generating circuit.

Abstract: A semiconductor memory device includes control circuits for respectively controlling operation timings of respective sense amplifiers related to an odd-numbered bit line pair and related to an even-numbered bit line pair. The control circuits thus allow respective sense amplifiers provided for bit line pairs adjacent to each other to operate at different timings respectively.

Abstract: A semipermanent hair dye composition comprising (A) a direct dye, (B) a hydrocarbon oil and (C) polyoxyalkylene-modified dimethyl polysiloxane.

Abstract: The semiconductor memory device includes normal word lines, spare word lines and bit lines. Space between the spare word lines is made wider than the space between the normal word lines. Further, the space between the normal word line and the spare word line is also made wider. Thus possibility of contact defect caused by a foreign matter in the steps of manufacturing can be reduced. Further, the size of the storage node of a spare memory cell is made larger than that of the storage node of a normal memory cell. Thus capacitance of the spare memory cell can be increased. Thus possibility of defects in spare memory cells is reduced ensuring repairment.

Abstract: A VBL generation circuit which normally outputs an equalizing potential outputs a potential corresponding to writing data in the test mode and this potential is collectively supplied to the bit lines by an equalizing circuit. In the test mode, a row decoder collectively activates the selected word lines by setting the pre-decode signals RX0 to RX3 to the active condition and by controlling the pre-decode signals X0 to X3 in accordance with the test signal. Accordingly, a writing in of a test pattern, wherein the detection of a short circuit between the storage nodes of memory cells is possible, can be carried out rapidly.

Abstract: A semiconductor memory device includes control circuits for respectively controlling operation timings of respective sense amplifiers related to an odd-numbered bit line pair and related to an even-numbered bit line pair. The control circuits thus allow respective sense amplifiers provided for bit line pairs adjacent to each other to operate at different timings respectively.

Abstract: A VBL generation circuit which normally outputs an equalizing potential outputs a potential corresponding to writing data in the test mode and this potential is collectively supplied to the bit lines by an equalizing circuit. In the test mode, a row decoder collectively activates the selected word lines by setting the pre-decode signals RX0 to RX3 to the active condition and by controlling the pre-decode signals X0 to X3 in accordance with the test signal. Accordingly, a writing in of a test pattern, wherein the detection of a short circuit between the storage nodes of memory cells is possible, can be carried out rapidly.

Abstract: A test on a desired internal voltage is easily and accurately conducted without increasing current dissipation or the number of pads. A driving circuit receiving a reference voltage from a reference voltage generating circuit has a high input impedance and low output impedance, and generates a voltage substantially at the same voltage level as the reference voltage received, and transmits the generated voltage to a pad with a current driving capability larger than the driving current capability of the reference voltage generating circuit.

Abstract: The semiconductor memory device includes normal word lines, spare word lines and bit lines. Space between the spare word lines is made wider than the space between the normal word lines. Further, the space between the normal word line and the spare word line is also made wider. Thus possibility of contact defect caused by a foreign matter in the steps of manufacturing can be reduced. Further, the size of the storage node of a spare memory cell is made larger than that of the storage node of a normal memory cell. Thus capacitance of the spare memory cell can be increased. Thus possibility of defects in spare memory cells is reduced ensuring repairment.

Abstract: A test on a desired internal voltage is easily and accurately conducted without increasing current dissipation or the number of pads. A driving circuit receiving a reference voltage from a reference voltage generating circuit has a high input impedance and low output impedance, and generates a voltage substantially at the same voltage level as the reference voltage received, and transmits the generated voltage to a pad with a current driving capability larger than the driving current capability of the reference voltage generating circuit.

Abstract: The semiconductor memory device includes normal word lines, spare word lines and bit lines. Space between the spare word lines is made wider than the space between the normal word lines. Further, the space between the normal word line and the spare word line is also made wider. Thus possibility of contact defect caused by a foreign matter in the steps of manufacturing can be reduced. Further, the size of the storage node of a spare memory cell is made larger than that of the storage node of a normal memory cell. Thus capacitance of the spare memory cell can be increased. Thus possibility of defects in spare memory cells is reduced ensuring repairment.

Abstract: A refresh operation is started in response to activation of a refresh control signal. The refresh control circuit controls activation of a refresh control signal in accordance with a signal level of a row address decode enable signal in addition to signal levels of control signals activated in response to activation of signals /CAS and /RAS necessary for detecting the start of a CBR refresh operation. The row address decode enable signal is an internal control signal activated upon activation of a signal /RAS and maintained in an active state until signal /RAS is inactivated. As a result, the refresh control signal is not erroneously activated during normal operation even when a noise is caused to signal /RAS.

Abstract: There is provided a test mode decision circuit which in the first WCBR cycle responds to an address key by activating a test mode entry signal and with the test mode entry signal activated in the second WCBR cycle responds to an address key by selectively activating test mode signals. In addition to a test mode signal having been activated, the test mode decision circuit further activates another test mode signal. Thus the DRAM hardly enter a test mode erroneously and is also capable of entering more than one test mode simultaneously.

Abstract: A semiconductor storage device capable of detecting a high resistance shortcircuit between a storage node of a memory cell and a gate in a transistor of the memory cell. A sense amplifier activating signal generating circuit section 13 in a ROW control section 2 delays, by a predetermined time, a timing for activating sense amplifier activating signals SON and ZSOP in a test mode in which a High-level test mode signal TM is input, delays, by a predetermined time, a timing for activating each of the sense amplifiers of the sense amplifier section 3, and detects a high resistance shortcircuit caused between a storage node SN in the memory cell and a gate TG of the transistor.

Abstract: The present invention provides a hair treatment composition (I) comprising the following components (a) and (b), or a hair treatment composition (II) comprising the following components (c) and (b), and a method for imparting elasticity to the hair using the composition: (a) an organic solvent; (b) at least one aromatic sulfonic acid selected from naphthalenesulfonic acids, azulenesulfonic acids, tetralin-sulfonic acids, indansulfonic acids and benzophenonesulfonic acids or salts thereof; and (c) a reducing agent.

Abstract: In a hair cosmetic containing titanium-dioxide-coated mica, titanium-dioxide-coated mica with particle diameters of 20 &mgr;m or larger is used in a proportion not more than 10% by volume in the total volume of the titanium-dioxide-coated mica so that, when applied to hair, it may not impart an unnaturally glittering impression to the hair. To improve re-dispersibility of such a hair cosmetic, a carboxyvinyl polymer and an amphoteric macromolecule may be used in combination.

Abstract: A semiconductor integrated circuit device includes an internal voltage-down converter and a voltage compensation circuit. The internal voltage-down converter provides an internal power supply voltage. The voltage compensation circuit includes a comparator, a capacitor, a transistor, and a constant current source. When the voltage (internal power supply voltage) of the output node suddenly drops, the potential at the positive input of the comparator is reduced by the coupling effect of the capacitor. As a result, the output node is charged. The potential of the positive input of the comparator is charged. As a result, the charging with respect to the output node ends.

Abstract: In a switchable multi bit DRAM, in addition to main bit line pair and a main sense amplifier, sub bit line pair and a sub sense amplifier are provided. Between the main bit line pair and the sub bit line pair, transistors are connected, and a transistor, a reference capacitor and a transistor are connected between the main bit line and the complementary sub bit line. By controlling these components, it becomes possible to use the memory cell as a 4-value memory or a binary memory. Therefore, storage capacity and power consumption can be switched.

Abstract: When memory storage capacity is required and power consumption is not so important, a semiconductor memory device is operated in a normal mode. When memory capacity is not so important and power consumption is to be suppressed, two memory cells are used connected in common to one bit line to store one data by rendering two word lines active at the same time. Accordingly, an operation of low power consumption with a longer refresh cycle is allowed. The user can appropriately switch between the two operation modes as necessary for usage.

Abstract: A synchronous DRAM includes a mode register, and a logic circuit controlling the drivability of a CMOS output buffer circuit in response to a signal which is set in the mode register. The output buffer circuit includes a plurality of P channel MOS transistors and an N channel MOS transistor. A signal which corresponds to the frequency of an external clock signal is set in the mode register. The logic circuit selectively turns on/off the plurality of P channel MOS transistors. When the frequency is low, the number of transistors which are turned on is reduced, and the drivability of the buffer circuit is lowered. Accordingly, a ringing phenomenon is suppressed.