Patents by Inventor Takashi Iwadare

Takashi Iwadare has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10290577
    Abstract: A SOP has a semiconductor chip. The chip includes a pair of a lower layer coil and an upper layer coil laminated through an interlayer insulating film formed therebetween, a first circuit unit electrically coupled to the upper layer coil, and a plurality of electrode pads. Further, it has a wire for electrically coupling the upper layer coil and the first circuit unit, a plurality of inner leads and outer leads arranged around the semiconductor chip, a plurality of wires for electrically coupling the electrode pads of the semiconductor chip and the inner leads, and a resin made sealing member for covering the semiconductor chip. The wire extends along the extending direction of the wires.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: May 14, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Teruhiro Kuwajima, Akira Matsumoto, Yasutaka Nakashiba, Takashi Iwadare
  • Publication number: 20180294222
    Abstract: A SOP has a semiconductor chip. The chip includes a pair of a lower layer coil and an upper layer coil laminated through an interlayer insulating film formed therebetween, a first circuit unit electrically coupled to the upper layer coil, and a plurality of electrode pads. Further, it has a wire for electrically coupling the upper layer coil and the first circuit unit, a plurality of inner leads and outer leads arranged around the semiconductor chip, a plurality of wires for electrically coupling the electrode pads of the semiconductor chip and the inner leads, and a resin made sealing member for covering the semiconductor chip. The wire extends along the extending direction of the wires.
    Type: Application
    Filed: June 15, 2018
    Publication date: October 11, 2018
    Inventors: Teruhiro KUWAJIMA, Akira MATSUMOTO, Yasutaka NAKASHIBA, Takashi IWADARE
  • Patent number: 10026689
    Abstract: A SOP has a semiconductor chip. The chip includes a pair of a lower layer coil and an upper layer coil laminated through an interlayer insulating film formed therebetween, a first circuit unit electrically coupled to the upper layer coil, and a plurality of electrode pads. Further, it has a wire for electrically coupling the upper layer coil and the first circuit unit, a plurality of inner leads and outer leads arranged around the semiconductor chip, a plurality of wires for electrically coupling the electrode pads of the semiconductor chip and the inner leads, and a resin made sealing member for covering the semiconductor chip. The wire extends along the extending direction of the wires.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: July 17, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Teruhiro Kuwajima, Akira Matsumoto, Yasutaka Nakashiba, Takashi Iwadare
  • Publication number: 20170062332
    Abstract: A SOP has a semiconductor chip. The chip includes a pair of a lower layer coil and an upper layer coil laminated through an interlayer insulating film formed therebetween, a first circuit unit electrically coupled to the upper layer coil, and a plurality of electrode pads. Further, it has a wire for electrically coupling the upper layer coil and the first circuit unit, a plurality of inner leads and outer leads arranged around the semiconductor chip, a plurality of wires for electrically coupling the electrode pads of the semiconductor chip and the inner leads, and a resin made sealing member for covering the semiconductor chip. The wire extends along the extending direction of the wires.
    Type: Application
    Filed: June 20, 2016
    Publication date: March 2, 2017
    Inventors: Teruhiro KUWAJIMA, Akira MATSUMOTO, Yasutaka NAKASHIBA, Takashi IWADARE
  • Patent number: 8373251
    Abstract: A first semiconductor chip includes a first inductor and a second inductor, and a second semiconductor chip includes a third inductor and a fourth inductor. The first inductor is connected to a first receiving circuit of the first semiconductor chip, and the second inductor is connected to a second transmitting circuit of the second semiconductor chip through a first bonding wire. The third inductor is connected to a second receiving circuit of the second semiconductor chip, and the fourth inductor is connected to a first transmitting circuit of the first semiconductor chip through a second bonding wire.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: February 12, 2013
    Assignees: Renesas Electronics Corporation, Toyota Jidosha Kabushiki Kaisha
    Inventors: Shinichi Uchida, Masayuki Furumiya, Hiroshi Sakakibara, Takashi Iwadare, Yoshiyuki Sato, Makoto Eguchi, Masato Taki, Hidetoshi Morishita, Kozo Kato, Jun Morimoto
  • Publication number: 20100230782
    Abstract: A first semiconductor chip includes a first inductor and a second inductor, and a second semiconductor chip includes a third inductor and a fourth inductor. The first inductor is connected to a first receiving circuit of the first semiconductor chip, and the second inductor is connected to a second transmitting circuit of the second semiconductor chip through a first bonding wire. The third inductor is connected to a second receiving circuit of the second semiconductor chip, and the fourth inductor is connected to a first transmitting circuit of the first semiconductor chip through a second bonding wire.
    Type: Application
    Filed: March 10, 2010
    Publication date: September 16, 2010
    Applicants: NEC ELECTRONICS CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shinichi UCHIDA, Masayuki FURUMIYA, Hiroshi SAKAKIBARA, Takashi IWADARE, Yoshiyuki SATO, Makoto EGUCHI, Masato TAKI, Hidetoshi MORISHITA, Kozo KATO, Jun MORIMOTO