Patents by Inventor Takashi Iwakiri

Takashi Iwakiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11976667
    Abstract: A centrifugal compressor comprises: an impeller; an inlet pipe portion forming an intake passage to introduce air to the impeller; and a throttle mechanism capable of reducing a flow passage area of the intake passage upstream of the impeller. The throttle mechanism includes an annular portion configured to move between a first position and a second position upstream of the first position in an axial direction of the impeller. In a cross-section along a rotational axis of the impeller, an outer peripheral surface of the annular portion is formed to smoothly connect a leading edge and a trailing edge of the annular portion.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: May 7, 2024
    Assignee: MITSUBISHI HEAVY INDUSTRIES ENGINE & TURBOCHARGER, LTD.
    Inventors: Kenichiro Iwakiri, Isao Tomita, Masaki Tojo, Takashi Yoshimoto
  • Patent number: 8896984
    Abstract: A solid electrolytic capacitor includes a capacitor element including a cathode portion and an anode portion, a cathode terminal bonded to the cathode portion, an anode terminal bonded to the anode portion, and an enclosure resin covering the capacitor element. The cathode terminal includes a cathode lower surface portion, a cathode connection portion, and a cathode support portion. The cathode connection portion is connected to an end portion of the cathode lower surface portion on an anode side and bonded to the cathode portion through a conductive adhesive. The cathode support portion is connected to a side portion of the cathode lower surface and brought into contact with a lower surface of the cathode portion on an end portion side of the cathode portion without involving the conductive adhesive therebetween.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: November 25, 2014
    Assignee: Panasonic Corporation
    Inventors: Kazuo Kawahito, Takashi Iwakiri
  • Publication number: 20100323835
    Abstract: A V-ribbed belt 10 includes a bottom rubber layer 12, an adhesive rubber layer 16, and a fabric 22. The bottom rubber layer 12 includes short fibers 14, a part of which protrude from the friction surface 12S of the bottom rubber layer 12. In the bottom rubber layer 12, an FEF carbon black with an average nitrogen adsorption surface area (ASTM D1765-01) of below 49 (m2/g), is used as a reinforcement. Therefore, the friction surface 12S of the bottom rubber layer 12 is slightly uneven, thus preventing the generation of an abnormal noise under usage of the V-ribbed belt 10. Further, after the short fibers 14 protruding from the friction surface 12S of the bottom rubber layer 12 have worn down, the unevenness of the friction surface 12S can be properly maintained by using such a carbon black, so that abnormal noise can be prevented.
    Type: Application
    Filed: February 20, 2008
    Publication date: December 23, 2010
    Inventors: Satoshi Furukawa, Toshihiko Kojima, Takashi Iwakiri, Kazuma Yamamoto
  • Patent number: 7365961
    Abstract: A solid electrolytic capacitor includes a planar solid electrolytic capacitor element having anode and cathode portions; anode and cathode terminals; and insulating coating resin. The anode terminal is electrically connected at the top surface thereof to the anode portion. The cathode terminal is electrically connected at the top surface side thereof to the cathode portion. The coating resin integrally coats the capacitor element so as to expose the bottom surfaces of the anode and cathode terminals. The anode and cathode terminals are disposed as close to each other as not more than 3 mm. The anode and cathode terminals have stair steps on both sides thereof and are connected to the anode and cathode portions at joint faces, respectively. The anode joint faces and the cathode joint faces are coated with coating resin. The solid electrolytic capacitor is provided with the anode joint faces and/or the cathode joint faces.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: April 29, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Junichi Kurita, Tsuyoshi Yoshino, Hirotoshi Toji, Kazuo Kawahito, Takashi Iwakiri, Hiroshi Serikawa, Kenji Kuranuki
  • Publication number: 20080002335
    Abstract: A solid electrolytic capacitor includes a planar solid electrolytic capacitor element having anode and cathode portions; anode and cathode terminals; and insulating coating resin. The anode terminal is electrically connected at the top surface thereof to the anode portion. The cathode terminal is electrically connected at the top surface side thereof to the cathode portion. The coating resin integrally coats the capacitor element so as to expose the bottom surfaces of the anode and cathode terminals. The anode and cathode terminals are disposed as close to each other as not more than 3 mm. The anode and cathode terminals have stair steps on both sides thereof and are connected to the anode and cathode portions at joint faces, respectively. The anode joint faces and the cathode joint faces are coated with coating resin. The solid electrolytic capacitor is provided with the anode joint faces and/or the cathode joint faces.
    Type: Application
    Filed: October 11, 2005
    Publication date: January 3, 2008
    Inventors: Junichi Kurita, Tsuyoshi Yoshino, Hirotoshi Toji, Kazuo Kawahito, Takashi Iwakiri, Hiroshi Serikawa, Kenji Kuranuki
  • Patent number: 6236561
    Abstract: A chip type solid electrolytic capacitor of the present invention has a section formed in a step-wise manner on a cathode lead frame that is connected with a capacitor element. An anode lead wire of the capacitor element is resistance welded to the top of a reversed V-letter shaped structure formed by folding part of an anode lead frame into halves. Further, with the chip type solid electrolytic capacitor of the present invention, part of respective cathode and anode lead frames is exposed outside in such a way as being made flush with the periphery of a resin package, thereby each serving as a terminal. Accordingly, a space problem due to the terminals has been eliminated and the anode lead wire can be made short, thus allowing the volume of a capacitor element employed to be increased. As a result, a chip type solid electrolytic capacitor having a large capacity with its outer dimensions is kept the same as a prior art capacitor can be obtained.
    Type: Grant
    Filed: June 16, 1999
    Date of Patent: May 22, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masakuni Ogino, Masahiro Yabushita, Koji Ueoka, Takashi Iwakiri, Tsuyoshi Yoshino
  • Patent number: 6130126
    Abstract: The dummy oxide used to form DRAM capacitor cells is left in place over the peripheral transistors, reducing the height difference between the DRAM array and the peripheral circuitry and protecting against edge effects.
    Type: Grant
    Filed: June 24, 1999
    Date of Patent: October 10, 2000
    Assignee: Texas Instruments Incorporated
    Inventor: Takashi Iwakiri
  • Patent number: 5629225
    Abstract: A manufacturing method for a dynamic RAM containing a screen-type structure cylindrical stack cell capacitor. An SiO.sub.2 layer 22 is formed on a polysilicon layer 11 (or a semiconductor substrate 1) to serve as a preform or spacer. A nitride layer 31 is stacked on this SiO.sub.2 layer, and nitride layer 31 and SiO.sub.2 layer 22 are worked into virtually the same pattern. Then the outside surface of SiO.sub.2 layer 22 is etched using nitride layer 31 as a mask, causing the nitride layer 31 to form a lateral projection structure 31A in the region removed by the etching. A polysilicon layer 23 is adhered to the top of silicon layer 11, which serves as a capacitor lower electrode, from the top of nitride layer 31 and SiO.sub.2 layer 22, including this projected portion. Polysilicon layer 23 is etched to leave a portion of polysilicon layer 23 on the outside surface of SiO.sub.2 layer 22 directly beneath the projecting portion 31A of nitride layer 31.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: May 13, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Takashi Iwakiri, Kiyomi Hirose, Hiroto Shinozuka, Osaomi Enomoto, Yasuhiro Okumoto
  • Patent number: D569799
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: May 27, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuo Kawahito, Kenji Kuranuki, Junichi Kurita, Takashi Iwakiri