Patents by Inventor Takashi Izumida
Takashi Izumida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11694995Abstract: A semiconductor memory device, includes: a first region including a memory cell array; and a second region including a peripheral circuit. The second region includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes: a semiconductor region between the first and second surfaces; an n-type semiconductor region provided on the first surface and higher in donor concentration than the semiconductor region; a damaged region provided on the second surface; and a p-type semiconductor region provided between the damaged region and the n-type semiconductor region, closer to the second surface than the n-type semiconductor region in a direction from the first surface toward the second surfaces of the semiconductor substrate, and higher in acceptor concentration than the semiconductor region.Type: GrantFiled: March 1, 2021Date of Patent: July 4, 2023Assignee: Kioxia CorporationInventors: Michihito Kono, Takashi Izumida, Tadayoshi Uechi, Takeshi Shimane
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Patent number: 11616072Abstract: According to one embodiment, a semiconductor memory device includes a first stacked body in which a plurality of first conductive layers are stacked at intervals in a first direction above a semiconductor substrate; a second stacked body in which a plurality of second conductive layers are stacked at intervals in the first direction above the semiconductor substrate; and a first slit extending in a second direction perpendicular to the first direction, the first slit isolating the first stacked body and the second stacked body in a third direction perpendicular to the first and second directions.Type: GrantFiled: March 23, 2022Date of Patent: March 28, 2023Assignee: Kioxia CorporationInventors: Tetsuya Yamashita, Takuyo Nakayama, Takashi Ichikawa, Tadayoshi Uechi, Takashi Izumida
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Patent number: 11527645Abstract: A semiconductor device of an embodiment includes: a first and second semiconductor regions of a first conductivity type; a third semiconductor region of a second conductivity type disposed between the first and second semiconductor regions; a fourth semiconductor region of the first conductivity type disposed below the first semiconductor region; a fifth semiconductor region of the first conductivity type disposed below the second semiconductor region; a first region containing carbon disposed between the first and fourth semiconductor regions; a second region containing carbon disposed between the second and fifth semiconductor regions; a third region disposed between the first and second regions; the first and second regions having a first and second carbon concentrations respectively, the third region not containing carbon or having a lower carbon concentration than the first and second carbon concentrations in a portion below an end of a lower face of a gate electrode.Type: GrantFiled: July 30, 2019Date of Patent: December 13, 2022Assignee: KIOXIA CORPORATIONInventors: Tadayoshi Uechi, Takashi Izumida, Takeshi Shimane
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Patent number: 11404572Abstract: According to one embodiment, a semiconductor device includes an element region, an element isolation region adjacent to the element region, a gate insulating layer provided on an upper surface of the element region, and a gate electrode including a semiconductor layer, the semiconductor layer containing boron (B) and including a portion provided on the gate insulating layer, the element isolation region including an upper portion including an upper surface of the element isolation region and a lower portion including a lower surface of the element isolation region, and the upper portion of the element isolation region applying compressive stress to a portion of the element region, which is adjacent to the upper portion of the element isolation region.Type: GrantFiled: March 12, 2020Date of Patent: August 2, 2022Assignee: KIOXIA CORPORATIONInventors: Tadayoshi Uechi, Takashi Izumida
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Publication number: 20220216228Abstract: According to one embodiment, a semiconductor memory device includes a first stacked body in which a plurality of first conductive layers are stacked at intervals in a first direction above a semiconductor substrate; a second stacked body in which a plurality of second conductive layers are stacked at intervals in the first direction above the semiconductor substrate; and a first slit extending in a second direction perpendicular to the first direction, the first slit isolating the first stacked body and the second stacked body in a third direction perpendicular to the first and second directions.Type: ApplicationFiled: March 23, 2022Publication date: July 7, 2022Applicant: Kioxia CorporationInventors: Tetsuya YAMASHITA, Takuyo NAKAYAMA, Takashi ICHIKAWA, Tadayoshi UECHI, Takashi IZUMIDA
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Patent number: 11355510Abstract: According to one embodiment, a semiconductor memory device includes a first stacked body in which a plurality of first conductive layers are stacked at intervals in a first direction above a semiconductor substrate; a second stacked body in which a plurality of second conductive layers are stacked at intervals in the first direction above the semiconductor substrate; and a first slit extending in a second direction perpendicular to the first direction, the first slit isolating the first stacked body and the second stacked body in a third direction perpendicular to the first and second directions.Type: GrantFiled: February 26, 2020Date of Patent: June 7, 2022Assignee: Kioxia CorporationInventors: Tetsuya Yamashita, Takuyo Nakayama, Takashi Ichikawa, Tadayoshi Uechi, Takashi Izumida
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Publication number: 20220084984Abstract: A semiconductor memory device, includes: a first region including a memory cell array; and a second region including a peripheral circuit. The second region includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes: a semiconductor region between the first and second surfaces; an n-type semiconductor region provided on the first surface and higher in donor concentration than the semiconductor region; a damaged region provided on the second surface; and a p-type semiconductor region provided between the damaged region and the n-type semiconductor region, closer to the second surface than the n-type semiconductor region in a direction from the first surface toward the second surfaces of the semiconductor substrate, and higher in acceptor concentration than the semiconductor region.Type: ApplicationFiled: March 1, 2021Publication date: March 17, 2022Applicant: Kioxia CorporationInventors: Michihito KONO, Takashi IZUMIDA, Tadayoshi UECHI, Takeshi SHIMANE
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Patent number: 11056558Abstract: A semiconductor device according to an embodiment includes a semiconductor layer having a first plane and a second plane opposite to the first plane; a gate electrode; a gate insulating layer provided between the first plane and the gate electrode; and a pair of first p-type impurity regions provided in the semiconductor layer on both sides of the gate electrode, containing boron, carbon, and germanium, having a bond structure of boron and carbon, having a first boron concentration and a first depth in a direction from the first plane toward the second plane, and having a distance between the first p-type impurity regions being a first distance.Type: GrantFiled: February 15, 2019Date of Patent: July 6, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takashi Izumida, Takeshi Shimane, Tadayoshi Uechi
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Publication number: 20210091044Abstract: According to one embodiment, a semiconductor memory device includes a first stacked body in which a plurality of first conductive layers are stacked at intervals in a first direction above a semiconductor substrate; a second stacked body in which a plurality of second conductive layers are stacked at intervals in the first direction above the semiconductor substrate; and a first slit extending in a second direction perpendicular to the first direction, the first slit isolating the first stacked body and the second stacked body in a third direction perpendicular to the first and second directions.Type: ApplicationFiled: February 26, 2020Publication date: March 25, 2021Applicant: Kioxia CorporationInventors: Tetsuya YAMASHITA, Takuyo NAKAYAMA, Takashi ICHIKAWA, Tadayoshi UECHI, Takashi IZUMIDA
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Publication number: 20210091221Abstract: According to one embodiment, a semiconductor device includes an element region, an element isolation region adjacent to the element region, a gate insulating layer provided on an upper surface of the element region, and a gate electrode including a semiconductor layer, the semiconductor layer containing boron (B) and including a portion provided on the gate insulating layer, the element isolation region including an upper portion including an upper surface of the element isolation region and a lower portion including a lower surface of the element isolation region, and the upper portion of the element isolation region applying compressive stress to a portion of the element region, which is adjacent to the upper portion of the element isolation region.Type: ApplicationFiled: March 12, 2020Publication date: March 25, 2021Applicant: Kioxia CorporationInventors: Tadayoshi UECHI, Takashi IZUMIDA
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Publication number: 20200295191Abstract: A semiconductor device of an embodiment includes: a first and second semiconductor regions of a first conductivity type; a third semiconductor region of a second conductivity type disposed between the first and second semiconductor regions; a fourth semiconductor region of the first conductivity type disposed below the first semiconductor region; a fifth semiconductor region of the first conductivity type disposed below the second semiconductor region; a first region containing carbon disposed between the first and fourth semiconductor regions; a second region containing carbon disposed between the second and fifth semiconductor regions; a third region disposed between the first and second regions; the first and second regions having a first and second carbon concentrations respectively, the third region not containing carbon or having a lower carbon concentration than the first and second carbon concentrations in a portion below an end of a lower face of a gate electrode.Type: ApplicationFiled: July 30, 2019Publication date: September 17, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Tadayoshi UECHI, Takashi IZUMIDA, Takeshi SHIMANE
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Publication number: 20200091292Abstract: A semiconductor device according to an embodiment includes a semiconductor layer having a first plane and a second plane opposite to the first plane; a gate electrode; a gate insulating layer provided between the first plane and the gate electrode; and a pair of first p-type impurity regions provided in the semiconductor layer on both sides of the gate electrode, containing boron, carbon, and germanium, having a bond structure of boron and carbon, having a first boron concentration and a first depth in a direction from the first plane toward the second plane, and having a distance between the first p-type impurity regions being a first distance.Type: ApplicationFiled: February 15, 2019Publication date: March 19, 2020Applicant: Toshiba Memory CorporationInventors: Takashi IZUMIDA, Takeshi SHIMANE, Tadayoshi UECHI
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Patent number: 10535712Abstract: A semiconductor device includes a substrate, a semiconductor layer, a first interconnection, a second interconnection and a control electrode. The semiconductor layer includes a first channel portion and a second channel portion. The first channel portion and the second channel portion extend in a first direction crossing a front surface of the substrate. The first interconnection is connected to one end of the semiconductor layer, and extends in a second direction along the front surface of the substrate. The second interconnection is connected to the other end of the semiconductor layer. The control electrode extends along the front surface of the substrate, and extends in a third direction crossing the second direction. The control electrode includes a portion positioned between the first channel portion and the second channel portion. The control electrode is electrically insulated from the semiconductor layer.Type: GrantFiled: September 11, 2018Date of Patent: January 14, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventor: Takashi Izumida
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Publication number: 20190288036Abstract: A semiconductor device includes a substrate, a semiconductor layer, a first interconnection, a second interconnection and a control electrode. The semiconductor layer includes a first channel portion and a second channel portion. The first channel portion and the second channel portion extend in a first direction crossing a front surface of the substrate. The first interconnection is connected to one end of the semiconductor layer, and extends in a second direction along the front surface of the substrate. The second interconnection is connected to the other end of the semiconductor layer. The control electrode extends along the front surface of the substrate, and extends in a third direction crossing the second direction. The control electrode includes a portion positioned between the first channel portion and the second channel portion. The control electrode is electrically insulated from the semiconductor layer.Type: ApplicationFiled: September 11, 2018Publication date: September 19, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventor: Takashi IZUMIDA
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Patent number: 10276590Abstract: According to one embodiment, a semiconductor device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed; a semiconductor body provided in the stacked body; and an insulating film. The semiconductor body includes a channel portion extending in a stacking direction of the stacked body, and a lower end portion of the semiconductor body provided between the channel portion and the substrate. The insulating film includes a charge storage film provided between the stacked body and the semiconductor body. A lower end portion of the insulating film surrounds the lower end portion of the semiconductor body. An upper surface of the lower end portion of the insulating film is provided at a lower height than an upper surface of the lower end portion of the semiconductor body in the stacking direction.Type: GrantFiled: February 14, 2018Date of Patent: April 30, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tatsufumi Hamada, Hikari Tajima, Takashi Izumida, Nobutoshi Aoki, Shinya Naito, Takayuki Kakegawa, Takaya Yamanaka
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Publication number: 20190013355Abstract: According to one embodiment, the first lines extend in a first direction. The first gate electrodes extend in a second direction intersecting with the first direction. The second lines extend in a third direction orthogonal to the first direction and the second direction. The semiconductor portion is disposed between the first gate electrodes, and between one of the first lines and one of the second lines, and connected to the first line and the second line. The semiconductor portion has a column shape. The semiconductor portion includes a plurality of channels isolated in a direction orthogonal to the third direction. The second gate electrode is provided between the channels. The insulating film is provided between the semiconductor portion and the first gate electrode, and between the semiconductor portion and the second gate electrode.Type: ApplicationFiled: February 27, 2018Publication date: January 10, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Hikari TAJIMA, Takashi IZUMIDA, Takahisa KANEMURA, Hiroki TOKUHIRA
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Publication number: 20180175056Abstract: According to one embodiment, a semiconductor device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed; a semiconductor body provided in the stacked body; and an insulating film. The semiconductor body includes a channel portion extending in a stacking direction of the stacked body, and a lower end portion of the semiconductor body provided between the channel portion and the substrate. The insulating film includes a charge storage film provided between the stacked body and the semiconductor body. A lower end portion of the insulating film surrounds the lower end portion of the semiconductor body. An upper surface of the lower end portion of the insulating film is provided at a lower height than an upper surface of the lower end portion of the semiconductor body in the stacking direction.Type: ApplicationFiled: February 14, 2018Publication date: June 21, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Tatsufumi HAMADA, Hikari TAJIMA, Takashi IZUMIDA, Nobutoshi AOKI, Shinya NAITO, Takayuki KAKEGAWA, Takaya YAMANAKA
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Patent number: 9917099Abstract: According to one embodiment, a semiconductor device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed; a semiconductor body provided in the stacked body; and an insulating film. The semiconductor body includes a channel portion extending in a stacking direction of the stacked body, and a lower end portion of the semiconductor body provided between the channel portion and the substrate. The insulating film includes a charge storage film provided between the stacked body and the semiconductor body. A lower end portion of the insulating film surrounds the lower end portion of the semiconductor body. An upper surface of the lower end portion of the insulating film is provided at a lower height than an upper surface of the lower end portion of the semiconductor body in the stacking direction.Type: GrantFiled: September 14, 2016Date of Patent: March 13, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tatsufumi Hamada, Hikari Tajima, Takashi Izumida, Nobutoshi Aoki, Shinya Naito, Takayuki Kakegawa, Takaya Yamanaka
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Patent number: 9871197Abstract: A semiconductor memory device according to an embodiment includes: a plurality of first conductive lines stacked in a first direction above a semiconductor substrate and extending in a second direction; a second conductive line extending in the first direction; semiconductor layers arranged between the first conductive lines and the second conductive line and extending in the first direction; a conductive layer in contact with a bottom surface of the semiconductor layer with a first impurity of a first conductivity type; and variable resistance films arranged at intersections between the first conductive lines and the semiconductor layer, the semiconductor layer having a first semiconductor part arranged from the bottom surface of the semiconductor layer to a position equal to or lower than a bottom surface of the first conductive line at a lowermost layer in the first direction with a second impurity of a second conductivity type.Type: GrantFiled: January 22, 2016Date of Patent: January 16, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hikari Tajima, Takashi Izumida
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Patent number: 9865656Abstract: A semiconductor memory device according to an embodiment includes a memory cell array that includes a plurality of memory cells.Type: GrantFiled: September 21, 2016Date of Patent: January 9, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takahisa Kanemura, Takashi Izumida