Abstract: A semiconductor memory device includes a memory cell, and first and second capacitive elements. The memory cell has a pair of inverters each including first and second driver nMOS transistors and first and second TFTs, and first and second access nMQS transistors. The first and second capacitive elements is connected to the drain of first and second access nMOS transistors, the drain of first and second driver nMOS transistors, and the drain of first and second TFTs. The gate width of first and second driver nMOS transistors is set at most 1.2 times longer than the gate width of first and second access nMOS transistors.

Abstract: In a memory cell, the cell ratio between an N-channel MOS transistor as a driver transistor and an N-channel MOS transistor as an access transistor is 1. To the first and second storage nodes, capacitors are connected, respectively. A word line driver receives a voltage obtained by boosting a power source voltage from a boosted power source voltage generating circuit and activates a word line with the boosted voltage. A bit line precharge circuit precharges bit lines to the power source potential when the word line is inactivated in accordance with a signal outputted from a BLPC signal generating circuit.

Abstract: A semiconductor memory device includes a memory cell, and first and second capacitive elements. The memory cell has a pair of inverters each including first and second driver nMOS transistors and first and second TFTs, and first and second access nMOS transistors. The first and second capacitive elements is connected to the drain of first and second access nMOS transistors, the drain of first and second driver nMOS transistors, and the drain of first and second TFTs. The gate width of first and second driver nMOS transistors is set at least 1.2 times longer than the gate width of first and second access nMOS transistors.

Abstract: In a memory cell, the cell ratio between an N-channel MOS transistor as a driver transistor and an N-channel MOS transistor as an access transistor is 1. To the first and second storage nodes, capacitors are connected, respectively. A word line driver receives a voltage obtained by boosting a power source voltage from a boosted power source voltage generating circuit and activates a word line with the boosted voltage. A bit line precharge circuit precharges bit lines to the power source potential when the word line is inactivated in accordance with a signal outputted from a BLPC signal generating circuit.

Abstract: During a burn-in test, each read selection gate, each write selection gate, a write control circuit, and a sense amplifier circuit are activated, and a read data bus precharge and equalize circuit and a global read data bus precharge and equalize circuit are inactivated. As a result, a voltage difference applied between a global write data bus pair is transferred to each of a write data bus pair, a bit line pair, a read data bus pair, and a global read data bus pair without involving a mode switching.

Abstract: During a burn-in test, each read selection gate, each write selection gate, a write control circuit, and a sense amplifier circuit are activated, and a read data bus precharge and equalize circuit and a global read data bus precharge and equalize circuit are inactivated. As a result, a voltage difference applied between a global write data bus pair is transferred to each of a write data bus pair, a bit line pair, a read data bus pair, and a global read data bus pair without involving a mode switching.

Abstract: A counter is provided in an SRAM using a CSP (Chip Scale Package). The counter includes n+1 stages of flipflops, counts the number of pulses of an address clock signal when a test signal attains “H” level, and outputs a group of address signals. Compared with a conventional SRAM to which the group of address signals is externally input, the number of external pins necessary when a test is conducted can be reduced, and a test board can be formed using a single-layer interconnection. Consequently, reduction of costs of testing is achieved.