Patents by Inventor Takashi Kaiga

Takashi Kaiga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9226050
    Abstract: A transmission apparatus includes a network-side interface unit configured to receive a signal transmission frame into which a client signal is arranged from each of a working line and a protection line of a network, and extract the client signal from the received signal transmission frame, a client-side interface unit configured to transmit the extracted client signal to a client transmission path by using a generated clock, based on frequency adjustment information of the client signal included in the signal transmission frame, a protection-line-side memory configured to store the frequency adjustment information of the client signal included in the signal transmission frame received from the protection line, and a switch controller configured to control to generate a clock by using the frequency adjustment information of the client signal stored in the protection-line-side memory when the signal transmission frame fails to be received from the working line.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: December 29, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Koichi Sugama, Masashige Kawarai, Hiroyuki Ishii, Yukio Katayanagi, Kenichi Hasegawa, Takashi Kaiga, Hiromitsu Yanaka, Tomohiro Ueno
  • Patent number: 8767802
    Abstract: A transmission device includes a receiver receiving a signal transmission frame from a network, where a client signal is mapped to the signal transmission frame; a separator separating the client signal from the signal transmission frame; a phase synchronizer generating a clock based on a frequency adjustment information set of the client information included in the signal transmission frame; a transmitter transmitting the client signal to a client transmission path by using the clock generated by the phase synchronizer; a memory storing the frequency adjustment information set included in the signal transmission frame in response to receiving the signal transmission frame from the network by the receiver; and a switch controller causing the phase synchronizer to generate a clock based on the frequency adjustment information set stored in the memory in response to not receiving the signal transmission frame from the network by the receiver.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: July 1, 2014
    Assignee: Fujitsu Limited
    Inventors: Yuichi Nagaki, Masashige Kawarai, Koichi Sugama, Tomohiro Ueno, Takashi Kaiga, Yukio Katayanagi
  • Publication number: 20130330075
    Abstract: A transmission apparatus includes a network-side interface unit configured to receive a signal transmission frame into which a client signal is arranged from each of a working line and a protection line of a network, and extract the client signal from the received signal transmission frame, a client-side interface unit configured to transmit the extracted client signal to a client transmission path by using a generated clock, based on frequency adjustment information of the client signal included in the signal transmission frame, a protection-line-side memory configured to store the frequency adjustment information of the client signal included in the signal transmission frame received from the protection line, and a switch controller configured to control to generate a clock by using the frequency adjustment information of the client signal stored in the protection-line-side memory when the signal transmission frame fails to be received from the working line.
    Type: Application
    Filed: April 30, 2013
    Publication date: December 12, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Koichi SUGAMA, Masashige Kawarai, Hiroyuki Ishii, Yukio Katayanagi, Kenichi Hasegawa, Takashi Kaiga, Hiromitsu Yanaka, Tomohiro Ueno
  • Publication number: 20120250739
    Abstract: A transmission device includes a receiver receiving a signal transmission frame from a network, where a client signal is mapped to the signal transmission frame; a separator separating the client signal from the signal transmission frame; a phase synchronizer generating a clock based on a frequency adjustment information set of the client information included in the signal transmission frame; a transmitter transmitting the client signal to a client transmission path by using the clock generated by the phase synchronizer; a memory storing the frequency adjustment information set included in the signal transmission frame in response to receiving the signal transmission frame from the network by the receiver; and a switch controller causing the phase synchronizer to generate a clock based on the frequency adjustment information set stored in the memory in response to not receiving the signal transmission frame from the network by the receiver.
    Type: Application
    Filed: March 20, 2012
    Publication date: October 4, 2012
    Applicant: Fujitsu Limited
    Inventors: Yuichi Nagaki, Masashige Kawarai, Koichi Sugama, Tomohiro Ueno, Takashi Kaiga, Yukio Katayanagi
  • Patent number: 7778160
    Abstract: A transmission device in which a bus of a central processing unit is used to synchronize timing signals between units, thereby restraining enlargement in scale of wiring. A reference signal generator generates a reference signal. A reference signal receiver is mounted on a unit set as an active or standby unit and receives the reference signal. A timing signal generator divides the frequency of the received reference signal by means of a frequency divider/counter to generate a timing signal. A count holder holds the count value of the frequency divider/counter. The bus connects the units and the central processing unit. A count receiver receives, via the bus, the count value from the count holder of the active unit. A count updater updates the count value of the frequency divider/counter to the count value received by the count receiver.
    Type: Grant
    Filed: July 19, 2007
    Date of Patent: August 17, 2010
    Assignee: Fujitsu Limited
    Inventors: Takashi Kaiga, Koichi Sugama, Tsutomu Chikazawa, Yukio Katayanagi, Kenichi Yajima, Hideo Abe, Ryuji Kayama, Masahiro Shioda
  • Patent number: 7639702
    Abstract: A plug-in card for an optical transmission apparatus includes a J1generating unit. The J1 generating unit sends information on on-use side J1 data to a plug-in card at a spare side in a redundant structure when the plug-in card operates as an on-use side plug-in card. The J1 generating unit receives information on on-use side J1 data from a plug-in card at the on-use side when the plug-in card operates as a spare side plug-in card. Based on the information, the J1 generating unit matches spare side J1 data to the on-use side J1 data. The plug-in card also includes a B3 byte calculating unit that operates in a similar way as the J1 generating unit does in processing B3 byte data.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: December 29, 2009
    Assignee: Fujitsu Limited
    Inventors: Hideki Matsui, Mitsuhiro Kawaguchi, Masahiro Shioda, Ryuji Kayama, Takashi Kaiga
  • Publication number: 20090237116
    Abstract: A receiving device for receiving a parallel-data including a clock and a plurality of data signals, the receiving device includes a plurality of data capturing circuits for receiving the data signal and the clock, respectively, the data capturing circuit capturing the data signal of the parallel-data on the bases of the clock; a plurality of phase comparing circuits for receiving the data signal and the clock, respectively, the phase comparing circuit capturing the clock of the parallel-data on the bases of the each data in order to compare a phase between the clock and the data signal; and an aggregating circuit for monitoring a relationship between the clock and the data signals on the bases of comparison results from the plurality of phase comparing circuits.
    Type: Application
    Filed: March 13, 2009
    Publication date: September 24, 2009
    Applicant: Fujitsu Limited
    Inventors: Hiroshi FUKAYA, Takashi Kaiga, Masaki Kubo
  • Patent number: 7408475
    Abstract: In a power supply monitoring device, a power supply voltage monitoring portion always monitors a power supply voltage supplied to a monitored circuit and outputs a voltage reduction signal when detecting that the power supply voltage is reduced below a predetermined threshold (e.g. a second voltage higher than a voltage guaranteeing a normal operation of the monitored circuit and lower than a rated voltage). A monitoring controller having received the voltage reduction signal determines whether or not an operational malfunction has occurred in the monitored circuit by comparing operation data of the monitored circuit with reference data of the monitoring controller itself. Also, the monitoring controller executes recovery processing (reset processing or reference data overwrite processing) suitable for the monitored circuit referring to a prestored recovery processing type specific to the monitored circuit when detecting an operational malfunction of the monitored circuit.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: August 5, 2008
    Assignee: Fujitsu Limited
    Inventors: Koichi Sugama, Noboru Shimizu, Tsutomu Chikazawa, Ryuji Kayama, Kenichi Yajima, Yukio Katayanagi, Takashi Kaiga
  • Publication number: 20080037592
    Abstract: A transmission device in which a bus of a central processing unit is used to synchronize timing signals between units, thereby restraining enlargement in scale of wiring. A reference signal generator generates a reference signal. A reference signal receiver is mounted on a unit set as an active or standby unit and receives the reference signal. A timing signal generator divides the frequency of the received reference signal by means of a frequency divider/counter to generate a timing signal. A count holder holds the count value of the frequency divider/counter. The bus connects the units and the central processing unit. A count receiver receives, via the bus, the count value from the count holder of the active unit. A count updater updates the count value of the frequency divider/counter to the count value received by the count receiver.
    Type: Application
    Filed: July 19, 2007
    Publication date: February 14, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Takashi Kaiga, Koichi Sugama, Tsutomu Chikazawa, Yukio Katayanagi, Kenichi Yajima, Hideo Abe, Ryuji Kayama, Masahiro Shioda
  • Publication number: 20070263646
    Abstract: A plug-in card for an optical transmission apparatus includes a J1 byte generating unit. The J1 byte generating unit sends information on on-use side J1 byte data to a plug-in card at a spare side in a redundant structure when the plug-in card operates as an on-use side plug-in card. The J1 byte generating unit receives information on on-use side J1 byte data from a plug-in card at the on-use side when the plug-in card operates as a spare side plug-in card. Based on the information, the J1 byte generating unit matches spare side J1 byte data to the on-use side J1 byte data. The plug-in card also includes a B3 byte calculating unit that operates in a similar way as the J1 byte generating unit does in processing B3 byte data.
    Type: Application
    Filed: September 28, 2006
    Publication date: November 15, 2007
    Inventors: Hideki Matsui, Mitsuhiro Kawaguchi, Masahiro Shioda, Ryuji Kayama, Takashi Kaiga
  • Publication number: 20070222630
    Abstract: In a power supply monitoring device, a power supply voltage monitoring portion always monitors a power supply voltage supplied to a monitored circuit and outputs a voltage reduction signal when detecting that the power supply voltage is reduced below a predetermined threshold (e.g. a second voltage higher than a voltage guaranteeing a normal operation of the monitored circuit and lower than a rated voltage). A monitoring controller having received the voltage reduction signal determines whether or not an operational malfunction has occurred in the monitored circuit by comparing operation data of the monitored circuit with reference data of the monitoring controller itself. Also, the monitoring controller executes recovery processing (reset processing or reference data overwrite processing) suitable for the monitored circuit referring to a prestored recovery processing type specific to the monitored circuit when detecting an operational malfunction of the monitored circuit.
    Type: Application
    Filed: July 24, 2006
    Publication date: September 27, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Koichi Sugama, Noboru Shimizu, Tsutomu Chikazawa, Ryuji Kayama, Kenichi Yajima, Yukio Katayanagi, Takashi Kaiga