Patents by Inventor Takashi Kanesaka

Takashi Kanesaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7137055
    Abstract: Semiconductor testing equipment according to the present invention comprises: an algorithmic pattern generator for generating a test pattern for testing a memory under test and applying the pattern to the memory under test; a comparator for comparing a response signal from the memory under test and an expected value from tho algorithmic pattern generator; a fail address acquisition part for storing an address of the memory under test (fail address) when a result compared by the comparator is failed; a fail address analysis part for analyzing the failed address and calculating the address to be repaired (repair address); and a cycle-pattern generator for redundancy processing for inserting the address to be repaired into a test pattern and applying the address to the memory under test, so that even when capacity of the semiconductor memory is increased, a fabrication yield thereof is raised by testing the memory after the packaging and by performing the redundancy processing of a defective.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: November 14, 2006
    Assignees: Hitachi, Ltd., Elpida Memory, Inc.
    Inventors: Katsunori Hirano, Shuji Kikuchi, Yuji Sonoda, Wen Li, Tadanobu Toba, Takashi Kanesaka, Masayuki Takahashi
  • Publication number: 20050149803
    Abstract: Semiconductor testing equipment according to the present invention comprises: an algorithmic pattern generator for generating a test pattern for testing a memory under test and applying the pattern to the memory under test; a comparator for comparing a response signal from the memory under test and an expected value from tho algorithmic pattern generator; a fail address acquisition part for storing an address of the memory under test (fail address) when a result compared by the comparator is failed; a fail address analysis part for analyzing the failed address and calculating the address to be repaired (repair address); and a cycle-pattern generator for redundancy processing for inserting the address to be repaired into a test pattern and applying the address to the memory under test, so that even when capacity of the semiconductor memory is increased, a fabrication yield thereof is raised by testing the memory after the packaging and by performing the redundancy processing of a defective.
    Type: Application
    Filed: December 16, 2004
    Publication date: July 7, 2005
    Inventors: Katsunori Hirano, Shuji Kikuchi, Yuji Sonoda, Wen Li, Tadanobu Toba, Takashi Kanesaka, Masayuki Takahashi
  • Publication number: 20030163359
    Abstract: An advertisement distributing apparatus 21 capable of sending e-mails to cellular telephones, which comprises a registrant file 41 for registering users possessing cellular telephones, a purchase history file 42 for compiling purchase histories, a behavior pattern file 43 for compiling the behaviors of registrants using GPS (Global Positioning Systems), a registrant needs file 44 comprising genres and the like set by registrants, and an advertisement request file 46 containing advertisement data to be distributed, and being constituted such that registrants to whom advertisements are to be distributed are extracted from purchase history file 42 and behavior pattern file 43, as well as from advertisement request file 46.
    Type: Application
    Filed: February 13, 2003
    Publication date: August 28, 2003
    Inventor: Takashi Kanesaka