Abstract: A decoder that decodes a current block using a motion vector includes: a processor; and memory. Using the memory, the processor: derives a first candidate vector from one or more candidate vectors of one or more neighboring blocks that neighbor the current block; determines, in a first reference picture for the current block, a first adjacent region that includes a position indicated by the first candidate vector; calculates evaluation values of a plurality of candidate regions included in the first adjacent region; and determines a first motion vector of the current block, based on a first candidate region having a smallest evaluation value among the evaluation values. The first adjacent region is included in a first motion estimation region determined based on the position indicated by the first candidate vector.

Abstract: According to one embodiment, there is provided an image data receiving device including 1st to Kth lane reproduction circuits, 1st to Kth timing adjustment circuits, 1st to Kth lane reproduction outputs, and 1st to (K?1)th selectors. The Nth lane reproduction circuit transmits data of an nth pixel. The (N+1)th lane reproduction circuit transmits data of an (n+1)th pixel adjacent to the nth pixel. The Nth timing adjustment circuit has an input terminal electrically connected to the Nth lane reproduction circuit. The (N+1)th timing adjustment circuit has an input terminal electrically connected to the (N+1)th lane reproduction circuit. The Nth lane reproduction output can be electrically connected to an output terminal of the Nth timing adjustment circuit. The Nth selector can electrically connect one of the output terminal of the Nth timing adjustment circuit and the output terminal of the (N+1)th timing adjustment circuit to the (N+1)th lane reproduction output.

Abstract: According to one embodiment, there is provided an image data receiving device including 1st to Kth lane reproduction circuits, 1st to Kth timing adjustment circuits, 1st to Kth lane reproduction outputs, and 1st to (K?1)th selectors. The Nth lane reproduction circuit transmits data of an nth pixel. The (N+1)th lane reproduction circuit transmits data of an (n+1)th pixel adjacent to the nth pixel. The Nth timing adjustment circuit has an input terminal electrically connected to the Nth lane reproduction circuit. The (N+1)th timing adjustment circuit has an input terminal electrically connected to the (N+1)th lane reproduction circuit. The Nth lane reproduction output can be electrically connected to an output terminal of the Nth timing adjustment circuit. The Nth selector can electrically connect one of the output terminal of the Nth timing adjustment circuit and the output terminal of the (N+1)th timing adjustment circuit to the (N+1)th lane reproduction output.

Abstract: According to an embodiment, an image processing device is operable by switching an operation mode among a first mode and a second mode. In the first mode, a first synchronization signal and a first image signal are inputted. The first synchronization signal comprising pulses having a first cycle, and the first image signal is composed of a plurality of frames switching in synchronization with the pulses of the first synchronization signal. In the second mode, an input of the first synchronization signal and the first image signal is stopped and a second image signal written to a frame memory is read.

Abstract: A color filter includes a red filter segment, a green filter segment and a blue filter segment, on a substrate, wherein when a pseudo-white LED is used, an area of a triangle defined by three chromaticity points of the red, green and blue filter segments expressed as (xR, yR), (xG, yG) and (xB, yB) on the x-y chromaticity diagram occupies 72% or more of an area standard triangle defined by defined by 3 points of red (0.67, 0.33), green (0.21, 0.71) and blue (0.14, 0.08), and the color filter has a color temperature of 6000K or more. Each of the red, green and blue filter segments has a thickness of 3.3 ?m or less. A liquid crystal display device includes such color filter and the pseudo-white LED.

Abstract: A receiving system includes: FIFO memory 13 storing audio data AD contained in a transmission signal T; an extraction unit 14 configured to extract a clock parameter contained in the transmission signal T; a parameter change unit 152 configured to change the clock parameter in accordance with a result of a comparison between a data storage rate SR of the FIFO memory 13 and a predetermined value; a frequency setting unit 153 configured to set a read frequency fr using the changed clock parameter; and a data read unit 16 configured to read the audio data AD from the FIFO memory 13 in synchronization with a reception end audio clock signal AC of the read frequency fr.

Abstract: A color filter includes a red filter segment, a green filter segment and a blue filter segment, on a substrate, wherein when a pseudo-white LED is used, an area of a triangle defined by three chromaticity points of the red, green and blue filter segments expressed as (xR, yR), (xG, yG) and (xB, yB) on the x-y chromaticity diagram occupies 72% or more of an area standard triangle defined by defined by 3 points of red (0.67, 0.33), green (0.21, 0.71) and blue (0.14, 0.08), and the color filter has a color temperature of 6000K or more. Each of the red, green and blue filter segments has a thickness of 3.3 ?m or less. A liquid crystal display device includes such color filter and the pseudo-white LED.

Abstract: A receiving system includes: FIFO memory 13 storing audio data AD contained in a transmission signal T; an extraction unit 14 configured to extract a clock parameter contained in the transmission signal T; a parameter change unit 152 configured to change the clock parameter in accordance with a result of a comparison between a data storage rate SR of the FIFO memory 13 and a predetermined value; a frequency setting unit 153 configured to set a read frequency fr using the changed clock parameter; and a data read unit 16 configured to read the audio data AD from the FIFO memory 13 in synchronization with a reception end audio clock signal AC of the read frequency fr.

Abstract: In a communication network, in which a plurality of switching nodes are connected with each other through a plurality of relay lines and one of the switching nodes acts as a center node for network routing, the center node estimates the state of delay of data for every relay line on the basis of information previously inputted, indicating the communication network configuration, and the state of delay of data reported by each of the switching nodes, and informs each of the switching nodes of said estimated state of delay of data. Each of the switching nodes determines and selects the relay line giving the shortest delay of data for every destination, to which it outputs data, on the basis of the state of delay at the relevant switching node itself and that received from the center node.