Abstract: Device miniaturization is made possible by building a battery protection circuit in a microcomputer. A secondary battery protection device includes a voltage detection device that detects a voltage of a power supply circuit including a secondary battery, a current detection device that detects a current of the power supply circuit, and a battery protection circuit that shuts off the power supply circuit based on a signal representing a detection made by the voltage detection device or the current detection device of an excess current that is generated in the power supply circuit. The protection circuit is built in a microcomputer.

Abstract: Device miniaturization is made possible by building a battery protection circuit in a microcomputer. A secondary battery protection device includes a voltage detection device that detects a voltage of a power supply circuit including a secondary battery, a current detection device that detects a current of the power supply circuit, and a battery protection circuit that shuts off the power supply circuit based on a signal representing a detection made by the voltage detection device or the current detection device of an excess current that is generated in the power supply circuit. The protection circuit is built in a microcomputer.

Abstract: Device miniaturization is made possible by building a battery protection circuit in a microcomputer. A secondary battery protection device includes a voltage detection device that detects a voltage of a power supply circuit including a secondary battery, a current detection device that detects a current of the power supply circuit, and a battery protection circuit that shuts off the power supply circuit based on a signal representing a detection made by the voltage detection device or the current detection device of an excess current that is generated in the power supply circuit. The protection circuit is built in a microcomputer.

Abstract: Device miniaturization is made possible by building a battery protection circuit in a microcomputer. A secondary battery protection device comprises a voltage detection means 7 that detects a voltage of a power supply circuit 6 including a secondary battery 1, a current detection means 8 that detects a current of the power supply circuit, and a battery protection circuit 10 that shuts off the power supply circuit 6 based on a signal representing a detection made by the voltage detection means 7 or the current detection means 8 of an excess current that is generated in the power supply circuit 6, wherein the protection circuit 10 is built in a microcomputer 13.

Abstract: There is provided a data processing device in which a ROM is mapped to an address space of a CPU only when a data storage region in a non-volatile memory is rewritten, to thereby facilitate rewriting the data storage region, and prevent a program storage region from being rewritten. A data processing device of the present invention is equipped with a CPU, a RAM, an address decoder, a flash memory and a mask ROM. When a data storage region in the flash memory is rewritten, the mask ROM is mapped while not being mapped in the other cases, whereby rewriting the data storage region is facilitated, and the program storage region is prevented from being rewritten.

Abstract: Device miniaturization is made possible by building a battery protection circuit in a microcomputer. A secondary battery protection device comprises a voltage detection means 7 that detects a voltage of a power supply circuit 6 including a secondary battery 1, a current detection means 8 that detects a current of the power supply circuit, and a battery protection circuit 10 that shuts off the power supply circuit 6 based on a signal representing a detection made by the voltage detection means 7 or the current detection means 8 of an excess current that is generated in the power supply circuit 6, wherein the protection circuit 10 is built in a microcomputer 13.

Abstract: A processor apparatus (microcomputer) 1 is equipped with a flash memory 17 which performs processing according to a processing program and rewriting for the flash memory. The flash memory-equipped processor apparatus comprises a mode switch register 18a that sets a normal mode that performs operations according to a processing program (application program) AP and a self-rewriting mode that performs rewriting operations for the flash memory during execution of the processing program. When processes in a self-rewriting mode are programmed in the processing program AP, a control device (CPU) 2 sets, during execution of the processing program AP, the mode switch register 18a to the self-rewriting mode, and performs a rewriting operation for the flash memory 17 according to a rewriting program (self-rewriting program) WP.

Abstract: There is provided a data processing device in which a ROM is mapped in an address space of a CPU only when a data storage region in a non-volatile memory is rewritten, to thereby facilitate rewriting the data storage region, and prevent a program storage region from being rewritten. A data processing device of the present invention is equipped with a CPU, a RAM, an address decoder, a flash memory and a mask ROM. When a data storage region in the flash memory is rewritten, the mask ROM is mapped while not being mapped in the other cases, whereby rewriting the data storage region is facilitated, and the program storage region is prevented from being rewritten.

Abstract: Accurate measurement results can be obtained without increasing the number of bits of a timer.A timer 1 performs counting with low-speed clocks immediately after input pulse is inputted. When the value counted by the timer with the low-speed clock coincides with the set value of a switching set value register 4, high-speed clocks are inputted to the timer 1 by a clock switching circuit 6 which is switched by the output of a comparison circuit 5.

Abstract: Accurate measurement results can be obtained without increasing the number of bits of a timer. A timer 1 performs counting with low-speed clocks immediately after input pulse is inputted. When the value counted by the timer with the low-speed clock coincides with the set value of a switching set value register 4, high-speed clocks are inputted. to the timer 1 by a clock switching circuit 6 which is switched by the output of a comparison circuit 5.