Patents by Inventor Takashi Katakura

Takashi Katakura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device having an ESD protection circuit
    Patent number: 9142543
    Abstract: An ESD protection circuit having a smaller area is provided. The ESD protection circuit includes: a P-type diffusion resistor 12 whose one end is connected to an input terminal 11 formed in the N-type well; a diode 14 disposed between the diffusion resistor 12 and the N-type well connected to the power supply terminal; an NMOS transistor 15 whose drain is connected to the other end of the diffusion resistor 12; and a parasitic diode formed between the power supply terminal and the ground terminal.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: September 22, 2015
    Assignee: SEIKO INSTRUMENTS INC.
    Inventors: Takashi Katakura, Hirofumi Harada, Yoshitsugu Hirose
  • SEMICONDUCTOR DEVICE HAVING AN ESD PROTECTION CIRCUIT
    Publication number: 20140217511
    Abstract: An ESD protection circuit having a smaller area is provided. The ESD protection circuit includes: a P-type diffusion resistor 12 whose one end is connected to an input terminal 11 formed in the N-type well; a diode 14 disposed between the diffusion resistor 12 and the N-type well connected to the power supply terminal; an NMOS transistor 15 whose drain is connected to the other end of the diffusion resistor 12; and a parasitic diode formed between the power supply terminal and the ground terminal.
    Type: Application
    Filed: February 4, 2014
    Publication date: August 7, 2014
    Applicant: SEIKO INSTRUMENTS INC.
    Inventors: Takashi KATAKURA, Hirofumi HARADA, Yoshitsugu HIROSE
  • SOI substrate, method of manufacture thereof, and semiconductor device using SOI substrate
    Patent number: 6558990
    Abstract: A manufacturing method of a SOI substrate (10) comprises the steps of: forming an oxide film (12) at cross-sectional both main surfaces and cross-sectional both end surfaces of a silicon substrate (11); forming a resist layer (13) on the oxide film (12) at cross-sectional both end surfaces of the substrate (11); and removing the oxide film (12) at those portions which are left from the covering of the resist layer (13), to thereby expose the both main surfaces of the substrate (11). Next, the resist layer (13) is removed to thereby leave the oxide film (12) at the both end surfaces of the substrate (11); and oxygen ions (I) are dosed into the substrate (11) from one of the exposed both main surfaces, followed by an anneal processing to thereby form an oxide layer (14) in a region at a predetermined depth from the one main surface of the substrate (11). The oxide film (12) left on the both end surfaces of the substrate (11) is then removed.
    Type: Grant
    Filed: March 1, 2001
    Date of Patent: May 6, 2003
    Assignees: Mitsubishi Materials Silicon Corporation, Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masaru Takamatsu, Takashi Katakura, Toshiaki Iwamatsu, Hideki Naruoka