Abstract: A method of manufacturing an epitaxially-strained lattice film of an oxide, in which epitaxially-strained lattices having a good crystalline property are formed by applying RF power to a substrate holder and irradiating positive ions having a moderate energy while preventing damage to the strained lattice film to be stacked by oxygen negative ions. This method simultaneously overcomes both the problem of damage to the film by irradiation of oxygen negative ions, which is peculiar to sputtering of oxides, and the problem of failure to strain due to relaxation of the strain during deposition.

Abstract: A ferroelectric capacitor comprising an Si substrate, a lower electrode including a metal film containing Ir or Rh and epitaxially grown on the Si substrate, and a conductive oxide film having a perovskite crystal structure and epitaxially grown on the metal film, a perovskite type ferroelectric thin film epitaxially grown on the lower electrode, and an upper electrode formed on the ferroelectric thin film. Alternatively, the lower electrode may be formed of a structure which comprises a silicide film represented by a chemical formula MSi2 (wherein M is at least one kind of transition metal selected from nickel, cobalt and manganese) and epitaxially grown on the Si substrate, a metal film containing Ir or Rh and epitaxially grown on the silicide film, and a conductive oxide film having a perovskite crystal structure and epitaxially grown on the metal film.

Abstract: A semiconductor memory device includes a memory cell constructed from an epitaxial planar capacitor and a switching transistor. The epitaxial planar capacitor includes a first and a second electrode layers and a dielectric thin film composed of ferroelectric or high dielectric material sandwiched between the first and the second electrode layers. Each of the constituent films of the epitaxial planar capacitors is epitaxial grown on a first main surface of a thin film semiconductor layer. And the switching transistor is formed in a second main surface of the thin film semiconductor layer. The second main surface faces to the first main surface. The memory cells are arranged in a matrix form to construct FRAM, DRAM or another semiconductor memory device. Employing perovskite crystal thin film serving as the dielectric thin film, a memory cell having a large capacity per unit area and high reliability is obtained. Then an ultrahigh density integration of semiconductor memory device is provided.

Abstract: A semiconductor integrated memory device comprises a plurality of memory cell blocks, which are formed in the form of a matrix and each of which comprises: a memory cell chain including a plurality of units, each comprising a ferroelectric memory capacitor and a control transistor connected in parallel thereto; a reference capacitor of a unit comprising a reference capacitor and a control transistor connected in parallel thereto; a read transistor having a gate electrode connected to a connection point between the memory cell chain and the reference cell; and a control transistor for adjusting potentials of storage node which is a connection point of the first electrode of the memory capacitor, the third electrode of the reference capacitor and the read transistor. With this construction, the semiconductor integrated memory device is able to be easily produced, to stably retain a ferroelectric polarization and to scale down.

Abstract: A method of manufacturing a semiconductor integrated memory device including a plurality of a memory cells, and the semiconductor memory device, wherein each memory cell includes a transistor and a capacitor. The capacitor is formed of first and second electrodes and a dielectric layer. The first electrode and the dielectric layer are successively formed on a main surface of a semiconductor substrate by epitaxial growth. A region of the capacitor is removed to expose a region of the main surface of the substrate under the capacitor. A single crystal semiconductor layer is formed on the exposed region of the substrate by epitaxial growth, and the transistor is formed on the single crystal semiconductor layer, thereby to obtain a device having high integration density integration and preferred performance with high yield.

Abstract: A sputtering system comprises: a substrate holder for holding a substrate; and a cathode having a magnet therein and holding a target, the cathode being off-axis aligned with respect to the substrate. The cathode may comprise a plurality of cathodes, each of which has a flat backing plate, and two targets supported on both sides of the backing plate, the target being off-axis aligned with respect to the thin-film deposited surface of the substrate. The target may be supported on the side surface of a cylindrical or prismatic cathode body having a magnet therein, and the target being off-axis aligned with respect to the thin-film deposited surface of the substrate.

Abstract: An electronic part comprising an amorphous thin film formed on a substrate; and a metal wiring formed on the surface of the amorphous thin film; wherein an interatomic distance corresponding to a peak of halo pattern appearing in diffraction measurement of the amorphous thin film approximately matches with a spacing of a particular crystal plane defined with the first nearest interatomic distance of the metal wiring. An electronic part provided with a metal wiring formed of highly orientated crystal wherein half or more of all grain boundaries are small angle grain boundaries defined by one of grain boundaries with a relative misorientation of 10.degree. or less in tilt, rotation and combination thereof around orientation axes of neighboring crystal grains; coincidence boundaries where a .SIGMA. value is 10 or less; and grain boundaries with a relative misorientation of 3.degree. or less from the coincidence boundary.

Abstract: A thin film capacitor comprises a dielectric thin film having a perovskite structure sandwiched between top and bottom electrodes. At least one of the top and bottom electrodes is made of a conductive oxide material having a perovskite structure represented with a general formula of ABO.sub.3 in which A represents A-site elements composed of at least two of alkaline-earth and rare earth metals, and B represents B-site elements composed of at least one of transition metals. The capacitors involve a small leakage current, occupy a small area, and provide large capacitance. Accordingly, the capacitors realize a high integration semiconductor memory such as a DRAM of gigabit order.

Abstract: A semiconductor memory device having a semiconductor substrate, an insulating layer provided on the substrate, and a memory cell. The memory cell has a switching transistor provided on the substrate and a charge storage element in a trench made in the insulating layer. The charge storage element has a bottom electrode, a dielectric layer and a top electrode deposited one on another in the order mentioned.

Abstract: A semiconductor memory device has a plurality of memory cells arranged in a matrix format. Each memory cell includes a thin film capacitor with a ferroelectric film and a pair of electrodes opposing each other through the ferroelectric film, and a transfer gate MOS transistor arranged to be connected to the thin film capacitor. The operating voltage value corresponding to the central axis of the polarization hysteresis characteristic curve of the thin film capacitor shifts from 0V by Vf. When no write or read operation is performed for the memory cell, the transistor is turned on, and an adjustment voltage set to be from 0 to 2 Vf is constantly applied across the electrodes of the thin film capacitor.

Abstract: A thin film capacitor including a first electrode having on its surface a (100) face of cubic system or a (001) face of tetragonal system, a dielectric thin film epitaxially grown on the first electrode and exhibiting a crystal structure which inherently belongs to a perovskite structure of cubic system, and a second electrode formed on the dielectric thin film. Further, the dielectric thin film meets the following relationship V/V.sub.0 .gtoreq.1.01 where a unit lattice volume of true perovskite crystal structure belonging to the cubic system (lattice constant a.sub.0) is represented by V.sub.0 =a.sub.0.sup.3, and a unit lattice volume (lattice constant a=b.noteq.c) which is strained toward a tetragonal system after the epitaxial growth is represented by V=a.sup.2 c, and also meets the following relationship c/a.gtoreq.1.01 where c/a represents a ratio between a lattice constant "c" in the direction thicknesswise of the film and a lattice constant "a" in the direction parallel with a plane of the film.

Abstract: A semiconductor memory device is constituted by arranging a plurality of memory cells in a matrix format, each of which includes a thin-film capacitor having a ferroelectric film and a pair of electrodes facing each other via the ferroelectric film, and a transfer gate transistor connected to the thin film capacitor. A voltage corresponding to the width of a hysteresis curve obtained when the thin-film capacitor is saturated and polarized falls within the range of 5% or higher to 20% or lower of the voltage difference between the positive and negative directions in a writing operation. A remanent polarization amount obtained when the thin-film capacitor is saturated and polarized falls within the range of 5% or higher to 30% or lower of the total polarization amount obtained upon application of a voltage in the writing operation.

Abstract: A nonvolatile semiconductor memory device has a ferroelectric cell and a paraelectric cell. The ferroelectric cell includes a first thin-film capacitor which has a first lower electrode formed on a substrate, a first dielectric film grown on the first lower electrode and a first upper electrode formed on the first dielectric film, and a first switching transistor connected to the first thin-film capacitor. The paraelectric cell includes a second thin-film capacitor which has a second lower electrode, a second dielectric film grown on the second lower electrode and a second upper electrode formed on the second dielectric film, and a second switching transistor connected to the second thin-film capacitor. The first lower electrode is provided such that the first dielectric film has ferroelectricities, while the second lower electrode is provided such that the second dielectric film has paraelectricities.

Abstract: A capacitor having a first electrode and a dielectric material epitaxially deposited on a surface of the electrode to form a dielectric layer on the electrode. The dielectric material forming the dielectric layer has induced strain in the layer sufficient to significantly improve the dielectric properties. A second electrode is placed on the dielectric layer.

Abstract: An image inspection device includes correlation calculating device for calculating a correlation value between sample image data and reference image data and correction device for correcting the sample image data according to the calculated correlation value. A comparator compares the corrected sample image data with the reference image data. The correlation value can be a correlation between an X-direction projection pattern and a Y-direction projection pattern, or the correlation value can be a density distribution correlation. With the projection pattern correlation, the read timing of the reference image data for the comparison is delayed according to the correlation value. With the density distribution correlation, the density distribution of the sample image data is corrected according to the correlation value.

Abstract: A semiconductor memory device comprising a silicon substrate, a plurality of switching transistors formed on the silicon substrate, an insulating layer having an opening and formed on a surface portion of the silicon substrate where the plurality of switching transistors formed, and a plurality of capacitors for accumulating electric charge formed on the insulating layer and connected respectively to the switching transistors via a conductive film buried in the opening of insulating layer, wherein each of the capacitors for accumulating electric charge is provided with an underlying crystal layer formed on the insulating layer and with a dielectric film consisting essentially of a ferroelectric material and epitaxially or orientationaly grown on the underlying crystal layer, and the switching transistors and the capacitors for accumulating electric charge connected to each other constitute a plurality of memory cells arranged in a two-dimensional pattern.

Abstract: An electronic part comprising an amorphous thin film formed on a substrate; and a metal wiring formed on the surface of the amorphous thin film; wherein an interatomic distance corresponding to a peak of halo pattern appearing in diffraction measurement of the amorphous thin film approximately matches with a spacing of a particular crystal plane defined with the first nearest interatomic distance of the metal wiring. An electronic part provided with a metal wiring formed of highly orientated crystal wherein half or more of all grain boundaries are small angle grain boundaries defined by one of grain boundaries with a relative misorientation of 10.degree. or less in tilt, rotation and combination thereof around orientation axes of neighboring crystal grains; coincidence boundaries where a .SIGMA. value is 10 or less; and grain boundaries with a relative misorientation of 3.degree. or less from the coincidence boundary.

Abstract: A semiconductor memory device having a semiconductor substrate, an insulating layer provided on the substrate, and a memory cell. The memory cell has a switching transistor provided on the substrate and a charge storage element in a trench made in the insulating layer. The charge storage element has a bottom electrode, a dielectric layer and a top electrode deposited one on another in the order mentioned.

Abstract: An electronic part is disclosed which is furnished with an artificial super lattice obtained by alternately superposing a substance of good conductivity formed of a compound between one element selected from among the elements belonging to the transition elements of Groups 3A to 6A and the rare earth elements and an element selected from among boron, carbon, nitrogen, phosphorus, selenium, and tellurium or a compound between oxygen and a transition metal element selected from among the elements of Group 7A and Group 8 and an insulating substance formed of a compound between a simple metal element selected from among the elements belonging to Group 1A, Group 2A, and Groups 1B to 4B and an element selected from among carbon, nitrogen, oxygen, phosphorus, sulfur, selenium, tellurium, and halogen elements in thicknesses fit for obtaining a quantum size effect.