Patents by Inventor Takashi Kawanoue
Takashi Kawanoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060060977Abstract: A semiconductor device includes a low dielectric constant insulating layer formed above a semiconductor substrate having an element region, and a Cu wiring isolated by the low dielectric constant insulating layer. Between the low dielectric constant insulating layer and the Cu wiring, there is disposed an ionization suppressing layer containing an element with a work function of less than 3 eV as a simple substance, a Cu concentration of the ionization suppressing layer being less than 10 atomic percent.Type: ApplicationFiled: September 22, 2005Publication date: March 23, 2006Inventor: Takashi Kawanoue
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Patent number: 6975033Abstract: A semiconductor device includes a semiconductor substrate on which an element is formed, a low dielectric constant insulation film formed over the semiconductor substrate and having a relative dielectric constant of 3 or lower, a plug and a wiring layer buried in the low dielectric constant insulation film, and a high Young's modulus insulation film having a Young's modulus of 15 GPa or higher and formed in contact with a side of the plug between the low dielectric constant insulation film and the plug.Type: GrantFiled: September 20, 2002Date of Patent: December 13, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Sachiyo Ito, Masahiko Hasunuma, Takashi Kawanoue
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Publication number: 20030116854Abstract: A semiconductor device comprises a semiconductor substrate on which an element is formed, a low dielectric constant insulation film formed over the semiconductor substrate and having a relative dielectric constant of 3 or lower, a plug and a wiring layer buried in the low dielectric constant insulation film, and a high Young's modulus insulation film having a Young's modulus of 15 GPa or higher and formed in contact with a side of the plug between the low dielectric constant insulation film and the plug.Type: ApplicationFiled: September 20, 2002Publication date: June 26, 2003Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Sachiyo Ito, Masahiko Hasunuma, Takashi Kawanoue
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Patent number: 6518177Abstract: A semiconductor device is formed by a compound film &agr;&ggr;x made of at least one element &agr; selected from metal elements and at least one element &ggr; selected from the group consisting of boron, carbon, and nitrogen on a base layer containing oxygen (O), and forming a compound film &agr;&ggr;yOz by causing the compound film &agr;&ggr;x to reduce the base layer and thereby oxidizing the compound film &agr;&ggr;x on an interface of the compound film &agr;&ggr;x and the base layer, wherein each of x and y is a ratio of the number of atoms of the element &ggr; to the number of atoms of the element &agr;, and z is a ratio of the number of atoms of the oxygen to the number of atoms of the element &agr;.Type: GrantFiled: February 15, 2001Date of Patent: February 11, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Kawanoue, Junichi Wada, Tetsuo Matsuda, Hisashi Kaneko
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Patent number: 6348402Abstract: A groove or hole is formed in an insulating layer formed on a semiconductor substrate, and a first conductive layer including a first metal element is formed on a surface of the insulating layer. By oxidizing the first conductive layer, an oxide layer of the first metal element is formed on a surface of the first conductive layer. A second conductive layer including a second metal element having a free energy of oxide formation lower than that of the first metal element is deposited thereon. By reducing the oxide layer of the first metal element by the second metal element, an oxide layer of the second metal element is formed at the interface between the first conductive layer and the second conductive layer. Further, an interconnection is buried in the groove or hole of the insulating layer.Type: GrantFiled: March 16, 2000Date of Patent: February 19, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Kawanoue, Tetsuo Matsuda, Hisashi Kaneko, Tadashi Iijima
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Patent number: 6229211Abstract: A semiconductor device comprises a base layer, a barrier metal layer formed on the base layer and a metal interconnect formed on the barrier metal layer, the barrier metal layer being made of at least one element &agr; selected from metal elements and at least one element &bgr; selected from a group of boron, oxygen, carbon and nitrogen and having at least two compound films &agr;&bgr;n with different compositional ratios in atomic level arranged to form a laminate. When the elements &agr; contained in the compound films &agr;&bgr;n are same and identical and at least one of the at least two compound films &agr;&bgr;n is a compound film &agr;&bgr;x (x>1), the via resistance and the interconnect resistance of the device can be reduced, while maintaining the high barrier effect.Type: GrantFiled: July 29, 1999Date of Patent: May 8, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Kawanoue, Junichi Wada, Tetsuo Matsuda, Hisashi Kaneko
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Patent number: 6001461Abstract: An electronic part comprising an amorphous thin film formed on a substrate; and a metal wiring formed on the surface of the amorphous thin film; wherein an interatomic distance corresponding to a peak of halo pattern appearing in diffraction measurement of the amorphous thin film approximately matches with a spacing of a particular crystal plane defined with the first nearest interatomic distance of the metal wiring. An electronic part provided with a metal wiring formed of highly orientated crystal wherein half or more of all grain boundaries are small angle grain boundaries defined by one of grain boundaries with a relative misorientation of 10.degree. or less in tilt, rotation and combination thereof around orientation axes of neighboring crystal grains; coincidence boundaries where a .SIGMA. value is 10 or less; and grain boundaries with a relative misorientation of 3.degree. or less from the coincidence boundary.Type: GrantFiled: December 19, 1996Date of Patent: December 14, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Toyoda, Hisashi Kaneko, Masahiko Hasunuma, Takashi Kawanoue, Hiroshi Tomita, Akihiro Kajita, Masami Miyauchi, Takashi Kawakubo, Sachiyo Ito
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Patent number: 5709958Abstract: An electronic part comprising an amorphous thin film formed on a substrate; and a metal wiring formed on the surface of the amorphous thin film; wherein an interatomic distance corresponding to a peak of halo pattern appearing in diffraction measurement of the amorphous thin film approximately matches with a spacing of a particular crystal plane defined with the first nearest interatomic distance of the metal wiring. An electronic part provided with a metal wiring formed of highly orientated crystal wherein half or more of all grain boundaries are small angle grain boundaries defined by one of grain boundaries with a relative misorientation of 10.degree. or less in tilt, rotation and combination thereof around orientation axes of neighboring crystal grains; coincidence boundaries where a .SIGMA. value is 10 or less; and grain boundaries with a relative misorientation of 3.degree. or less from the coincidence boundary.Type: GrantFiled: May 26, 1995Date of Patent: January 20, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Toyoda, Hisashi Kaneko, Masahiko Hasunuma, Takashi Kawanoue, Hiroshi Tomita, Akihiro Kajita, Masami Miyauchi, Takashi Kawakubo, Sachiyo Ito
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Patent number: 5498909Abstract: The close-packed plane of a single crystal forming an electrode line such as electrodes or lines of a semiconductor device whose active regions are reduced in size, i.e., highly integrated, is arranged parallel to the longitudinal direction of the line; or in the case of a polycrystalline electrode line, the angle formed between the normal line direction of the close-packed plane of its crystal grains and that of the electrode line is arranged to be 80.degree. or less.Type: GrantFiled: August 31, 1992Date of Patent: March 12, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Masahiko Hasunuma, Hisashi Kaneko, Atsuhito Sawabe, Takashi Kawanoue, Yoshiko Kohanawa, Shuichi Komatsu
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Patent number: 5187561Abstract: The close-packed plane of a single crystal forming an electrode line such as electrodes or lines of a semiconductor device whose active regions are reduced in size, i.e., highly integrated, is arranged parallel to the longitudinal direction of the line; or in the case of a polycrystalline electrode line, the angle formed between the normal line direction of the close-packed plane of its crystal grains and that of the electrode line is arranged to be 80.degree. or less.Type: GrantFiled: June 29, 1990Date of Patent: February 16, 1993Assignee: Kabushiki Kaisha ToshibaInventors: Masahiko Hasunuma, Hisashi Kaneko, Atsuhito Sawabe, Takashi Kawanoue, Yoshiko Kohanawa, Shuichi Komatsu