Abstract: A driver IC (100) includes a pair of output terminals in each of a plurality of channels and in each of the channels, power is supplied from the pair of output terminals (OUT1 and OUT2, OUT3 and OUT4, OUT5 and OUT6 or OUT7 and OUT8) to a load (M1, M2, M3 or M4). In each of the channels, the pair of output terminals are adjacent to each other.

Abstract: A driver IC (100) includes a pair of output terminals in each of a plurality of channels and in each of the channels, power is supplied from the pair of output terminals (OUT1 and OUT2, OUT3 and OUT4, OUT5 and OUT6 or OUT7 and OUT8) to a load (M1, M2, M3 or M4). In each of the channels, the pair of output terminals are adjacent to each other.

Abstract: In a RAM control device, an arbiter circuit is means for generating BUSY1 and BUSY2 of exclusive logic with CLK1 and CLK2 so as to give a right to access RAM3 to a host which has transmitted the first access clock and requesting a one-shot circuit to generate RAMCLK for deciding the timing to access the RAM3. The one-shot circuit is means for generating one pulse of RAMCLK with CLKRQ from the arbiter circuit and transmitting it to the RAM3. This configuration suppresses increase of the device size and cost and enables appropriate control of access to the RAM according to the access clocks of two systems inputted asynchronously.

Abstract: In a RAM control device, an arbiter circuit (1) is means for generating BUSY1 and BUSY2 of exclusive logic in accordance with CLK1 and CLK2 so as to give a right to access RAM3 to a host which has transmitted the first access clock and requesting a one-shot circuit (2) to generate RAMCLK for deciding the timing to access the RAM3. The one-shot circuit (2) is means for generating one pulse of RAMCLK in accordance with CLKRQ from the arbiter circuit (1) and transmitting it to the RAM3. This configuration suppresses increase of the device size and cost and enables appropriate control of access to the RAM according to the access clocks of two systems inputted asynchronously.