Patents by Inventor Takashi Kishida

Takashi Kishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11985452
    Abstract: A color conversion element includes: a substrate; a phosphor portion that is disposed above the substrate, receives laser light transmitted from an outside, and emits light in a color different from a color of the laser light; a reflective layer that includes a dielectric multilayer film and is disposed on a principal surface of the phosphor portion facing the substrate; and a joining portion interposed between the reflective layer and the substrate to join the reflective layer and the substrate. The joining portion includes an air layer that exposes the reflective layer in a position where the air layer at least partially overlaps an irradiation region in a plan view, the irradiation region being a region irradiated with the laser light on the phosphor portion.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: May 14, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takanori Aketa, Yosuke Honda, Takashi Kishida, Toru Hirano
  • Publication number: 20210344883
    Abstract: A color conversion element includes: a substrate; a phosphor portion that is disposed above the substrate, receives laser light transmitted from an outside, and emits light in a color different from a color of the laser light; a reflective layer that includes a dielectric multilayer film and is disposed on a principal surface of the phosphor portion facing the substrate; and a joining portion interposed between the reflective layer and the substrate to join the reflective layer and the substrate. The joining portion includes an air layer that exposes the reflective layer in a position where the air layer at least partially overlaps an irradiation region in a plan view, the irradiation region being a region irradiated with the laser light on the phosphor portion.
    Type: Application
    Filed: July 23, 2019
    Publication date: November 4, 2021
    Applicant: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Takanori AKETA, Yosuke HONDA, Takashi KISHIDA, Toru HIRANO
  • Patent number: 8779837
    Abstract: A load control device includes a switching unit which is connected to a power source and a load in series and has a switch device having a transistor structure, a control unit configured to control start-up and stop of the load, and a gate driving unit, which is electrically insulated from the control unit and outputs a gate driving signal to the gate electrode of the switch device. The control unit controls the gate driving unit to supply a higher driving power to the gate electrode of the switch device for a predetermined period of time starting at the start-up of the load than that in a steady state.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: July 15, 2014
    Assignee: Panasonic Corporation
    Inventors: Kiyoshi Gotou, Masanori Hayashi, Takashi Kishida, Kouji Yamato
  • Publication number: 20140012527
    Abstract: The present invention makes it possible to determine whether a mechanical component can be reused, without consulting a specialist, by: attaching to the mechanical component an IC tag that records identification information that includes at least one among the type, manufacturing time, manufacturing lot, and manufacturing history of the mechanical component, and that enables the identification information to be externally read by an electromagnetic method; recording, in the memory unit of an inspection device that can read the IC tag, inspection items corresponding to the identification information and the evaluation criteria of the inspection items; displaying an inspection item corresponding to the mechanical component on a display unit; obtaining result information from an input unit; and comparing the result information to the evaluation criteria and displaying, on the display unit, whether the part can be reused.
    Type: Application
    Filed: March 19, 2012
    Publication date: January 9, 2014
    Inventors: Naota Yamamoto, Takashi Ito, Takashi Kishida, Yoriko Kosaka
  • Publication number: 20130265096
    Abstract: A load control device includes a switching unit which is connected to a power source and a load in series and has a switch device having a transistor structure, a control unit configured to control start-up and stop of the load, and a gate driving unit, which is electrically insulated from the control unit and outputs a gate driving signal to the gate electrode of the switch device. The control unit controls the gate driving unit to supply a higher driving power to the gate electrode of the switch device for a predetermined period of time starting at the start-up of the load than that in a steady state.
    Type: Application
    Filed: June 5, 2013
    Publication date: October 10, 2013
    Inventors: Kiyoshi GOTOU, Masanori HAYASHI, Takashi KISHIDA, Kouji YAMATO
  • Patent number: 6847435
    Abstract: A laser distance measuring apparatus, for measuring the distance between objects existing in two directions at least as seen from the apparatus by using laser light, comprises two projectors for projecting laser beams along a specified projection axis toward each one of the objects, a photo detector for receiving reflected light of projection from each object, a distance measurement processor for measuring the distance from a reference point of the apparatus to each object on the basis of the reception signal to the projection by the photo detector, and a distance calculation processor for calculating the distance between the objects on the basis of the distance data measured by the distance measurement processor and the angle formed by two projection axes, in which the projection axis by one projector is variable in angle with respect to the other projector. Therefore, the distance between objects can be measured easily and at high precision by one distance measuring operation only.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: January 25, 2005
    Assignee: Matsushita Electric Works, Ltd.
    Inventors: Tatsuya Honda, Hiroshi Maeda, Takashi Kishida, Kazunari Yoshimura, Kazufumi Oogi, Hideshi Hamaguchi, Yoshimitsu Nakamura, Kuninori Nakamura
  • Publication number: 20040051860
    Abstract: A laser distance measuring apparatus, for measuring the distance between objects existing in two directions at least as seen from the apparatus by using laser light, comprises two projectors for projecting laser beams along a specified projection axis toward each one of the objects, a photo detector for receiving reflected light of projection from each object, a distance measurement processor for measuring the distance from a reference point of the apparatus to each object on the basis of the reception signal to the projection by the photo detector, and a distance calculation processor for calculating the distance between the objects on the basis of the distance data measured by the distance measurement processor and the angle formed by two projection axes, in which the projection axis by one projector is variable in angle with respect to the other projector. Therefore, the distance between objects can be measured easily and at high precision by one distance measuring operation only.
    Type: Application
    Filed: June 24, 2003
    Publication date: March 18, 2004
    Applicant: Matsushita Electric Works, Ltd.
    Inventors: Tatsuya Honda, Hiroshi Maeda, Takashi Kishida, Kazunari Yoshimura, Kazufumi Oogi, Hideshi Hamaguchi, Yoshimitsu Nakamura, Kuninori Nakamura
  • Patent number: 6580126
    Abstract: A solid state relay composed of a series connected pair of LDMOSFETs has a minimized output capacitance. Each LDMOSFET is configured to have a silicon layer of a first conductive type, a drain region of the first conductive type diffused in the top surface of the silicon layer, a well region of a second conductive type diffused in the silicon layer in a laterally spaced relation from the drain region, and a source region of the first conductive type diffused within the well region to define a channel extending between the source region and a confronting edge of the well region along the top surface of the silicon layer. Each LDMOSFET is of an SOI (Silicon-On-Insulator) structure composed of a silicon substrate placed on a supporting plate, a buried oxide layer on the silicon substrate, and the silicon layer on the buried oxide layer.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: June 17, 2003
    Assignee: Matsushita Electric Works, Ltd.
    Inventors: Masahiko Suzumura, Hitomichi Takano, Yuji Suzuki, Takashi Kishida, Yoshiki Hayasaki, Yoshifumi Shirai, Takeshi Yoshida, Yasunori Miyamoto
  • Patent number: 6448620
    Abstract: To provide a semiconductor device having a large allowable current, a demanded withstand voltage, and small output capacitance and resistance, the semiconductor device comprises a semiconductor layer formed on a semiconductor substrate, and the semiconductor layer includes a first conductivity type-drain region, a second conductivity type-well region apart from the drain region, a first conductivity type-source region in the well region apart from one end of the well region on the side of the drain region, a first conductivity type-drift region formed between one end of the well region and the drain region and in contact with the well region and the drain region, respectively, and a gate electrode formed spaced a gate oxide layer and on the well region located between the drift region and the source region; and the impurity concentration of the drift region decreases in the lateral direction and also in the vertical direction, respectively, as the distance from the drain region increases.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: September 10, 2002
    Assignee: Matsushita Electric Works, Ltd.
    Inventors: Yoshiki Hayasaki, Hitomichi Takano, Masahiko Suzumura, Yuji Suzuki, Yoshifumi Shirai, Takashi Kishida, Takeshi Yoshida, Takaaki Yoshihara
  • Patent number: 6373101
    Abstract: A solid state relay composed of a series connected pair of LDMOSFETs has a minimized output capacitance. Each LDMOSFET is configured to have a silicon layer of a first conductive type, a drain region of the first conductive type diffused in the top surface of the silicon layer, a well region of a second conductive type diffused in the silicon layer in a laterally spaced relation from the drain region, and a source region of the first conductive type diffused within the well region to define a channel extending between the source region and a confronting edge of the well region along the top surface of the silicon layer. Each LDMOSFET is of an SOI (Silicon-On-Insulator) structure composed of a silicon substrate placed on a supporting plate, a buried oxide layer on the silicon substrate, and the silicon layer on the buried oxide layer.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: April 16, 2002
    Assignee: Matsushita Electric Works
    Inventors: Masahiko Suzumura, Hitomichi Takano, Yuji Suzuki, Takashi Kishida, Yoshiki Hayasaki, Yoshifumi Shirai, Takeshi Yoshida, Yasunori Miyamoto
  • Publication number: 20010013624
    Abstract: To provide a semiconductor device having a large allowable current, a demanded withstand voltage, and small output capacitance and resistance, the semiconductor device comprises a semiconductor layer formed on a semiconductor substrate, and the semiconductor layer includes a first conductivity type-drain region, a second conductivity type-well region apart from the drain region, a first conductivity type-source region in the well region apart from one end of the well region on the side of the drain region, a first conductivity type-drift region formed between one end of the well region and the drain region and in contact with the well region and the drain region, respectively, and a gate electrode formed spaced a gate oxide layer and on the well region located between the drift region and the source region; and the impurity concentration of the drift region decreases in the lateral direction and also in the vertical direction, respectively, as the distance from the drain region increases.
    Type: Application
    Filed: December 22, 2000
    Publication date: August 16, 2001
    Applicant: Matsushita Electric Works, Ltd.
    Inventors: Yoshiki Hayasaki, Hitomichi Takano, Masahiko Suzumura, Yuji Suzuki, Yoshifumi Shirai, Takashi Kishida, Takeshi Yoshida, Takaaki Yoshihara
  • Patent number: 6211551
    Abstract: A solid state relay composed of a series connected pair of LDMOSFETs has a minimized output capacitance. Each LDMOSFET is configured to have a silicon layer of a first conductive type, a drain region of the first conductive type diffused in the top surface of the silicon layer, a well region of a second conductive type diffused in the silicon layer in a laterally spaced relation from the drain region, and a source region of the first conductive type diffused within the well region to define a channel extending between the source region and a confronting edge of the well region along the top surface of the silicon layer. Each LDMOSFET is of an SOI (Silicon-On-Insulator) structure composed of a silicon substrate placed on a supporting plate, a buried oxide layer on the silicon substrate, and the silicon layer on the buried oxide layer.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: April 3, 2001
    Assignee: Matsushita Electric Works, Ltd.
    Inventors: Masahiko Suzumura, Hitomichi Takano, Yuji Suzuki, Takashi Kishida, Yoshiki Hayasaki, Yoshifumi Shirai, Takeshi Yoshida, Yasunori Miyamoto
  • Patent number: 5780900
    Abstract: A thin film transistor of SOI (Silicon-On-Insulator) type includes a buried oxide layer formed on a semiconductor substrate, a silicon layer of a first conductive type formed on the buried oxide layer, and an upper oxide layer formed on the silicon layer. The silicon layer has a body region of a second conductive type, source region of the first conductive type, drain region of the first conductive type, and a drift region of the first conductive type. The silicon layer is formed with a first portion of a thickness T1 in which the doping region is formed, and a second portion of a thickness T2 in which the body region is formed to reach the buried oxide layer. When the thicknesses T1 and T2 are determined so as to satisfy the relationships:0.4 .mu.m<T1,0.4 .mu.m.ltoreq.T2.ltoreq.1.5 .mu.m, andT2<T1,The transistor exhibits an improved power dissipation, high breakdown voltage, and a low on-resistance, and also provides advantages in a manufacturing process of the transistor.
    Type: Grant
    Filed: October 17, 1996
    Date of Patent: July 14, 1998
    Assignee: Matsushita Electric Works, Inc.
    Inventors: Yuji Suzuki, Hitomichi Takano, Masahiko Suzumura, Yoshiki Hayasaki, Takashi Kishida, Yoshifumi Shirai
  • Patent number: 5053201
    Abstract: A process and apparatus for the preparation of a polyester, wherein a thin film polymerization apparatus having at least one columnar or cylindrical roller-shaped stirring vane rotating along and in close proximity to a substantially cylindrical vertical tank wall is used, and the stirring vane is caused to make an epicyclic movement along the tank wall in the circumferential direction thereof so that the direction of rotation is the same as the direction of revolution and a polyester-forming monomer and/or an oligomer thereof is dropped on the surface of the tank wall in the form of a thin film.
    Type: Grant
    Filed: September 5, 1986
    Date of Patent: October 1, 1991
    Assignee: Teijin Limited
    Inventors: Shinichi Yamauchi, Katsushi Sasaki, Eiji Matsumura, Yasuhiko Saito, Takashi Kishida
  • Patent number: 4351492
    Abstract: Polyester yarns spun from spinnerets are delivered to bobbins held on a bobbin holder in a winding apparatus through godet rollers which have mirror finished surfaces and axially grooved surfaces. Upon threading the yarns on the bobbins, the yarns are moved to the axially grooved surface from the mirror finished surfaces by means of a yarn displacing guide disposed upstream of the uppermost godet roller. The change in the tension in the yarn caused by the threading operation of the yarn is transmitted beyond the godet rollers, and entanglement of the yarn around the godet roller does not occur.
    Type: Grant
    Filed: November 2, 1979
    Date of Patent: September 28, 1982
    Assignee: Teijin Limited
    Inventors: Hideki Aoyama, Takashi Kishida
  • Patent number: 3971517
    Abstract: A guide roller is traversed substantially in parallel to the axis of an uprightly supported bobbin at a speed slow enough not to form appreciable twilled angles of a wound yarn. The yarn continuously extruded from a spinning apparatus at a speed higher than 2000 m/min is introduced substantially in parallel to the axis of the bobbin and changes its direction to right angles with respect to the axis of the bobbin while travelling through the guide roller. The guide roller traverses with shorter traverse strokes as the diameter of the wound yarn becomes larger.
    Type: Grant
    Filed: August 12, 1974
    Date of Patent: July 27, 1976
    Assignee: Teijin Limited
    Inventors: Yosio Matuura, Shoichi Murakami, Norihisa Yamaguchi, Takashi Kishida, Sadao Kadokura, Kiyoshi Imai