Patents by Inventor Takashi Kishida
Takashi Kishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11985452Abstract: A color conversion element includes: a substrate; a phosphor portion that is disposed above the substrate, receives laser light transmitted from an outside, and emits light in a color different from a color of the laser light; a reflective layer that includes a dielectric multilayer film and is disposed on a principal surface of the phosphor portion facing the substrate; and a joining portion interposed between the reflective layer and the substrate to join the reflective layer and the substrate. The joining portion includes an air layer that exposes the reflective layer in a position where the air layer at least partially overlaps an irradiation region in a plan view, the irradiation region being a region irradiated with the laser light on the phosphor portion.Type: GrantFiled: July 23, 2019Date of Patent: May 14, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Takanori Aketa, Yosuke Honda, Takashi Kishida, Toru Hirano
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Publication number: 20210344883Abstract: A color conversion element includes: a substrate; a phosphor portion that is disposed above the substrate, receives laser light transmitted from an outside, and emits light in a color different from a color of the laser light; a reflective layer that includes a dielectric multilayer film and is disposed on a principal surface of the phosphor portion facing the substrate; and a joining portion interposed between the reflective layer and the substrate to join the reflective layer and the substrate. The joining portion includes an air layer that exposes the reflective layer in a position where the air layer at least partially overlaps an irradiation region in a plan view, the irradiation region being a region irradiated with the laser light on the phosphor portion.Type: ApplicationFiled: July 23, 2019Publication date: November 4, 2021Applicant: Panasonic Intellectual Property Management Co., Ltd.Inventors: Takanori AKETA, Yosuke HONDA, Takashi KISHIDA, Toru HIRANO
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Patent number: 8779837Abstract: A load control device includes a switching unit which is connected to a power source and a load in series and has a switch device having a transistor structure, a control unit configured to control start-up and stop of the load, and a gate driving unit, which is electrically insulated from the control unit and outputs a gate driving signal to the gate electrode of the switch device. The control unit controls the gate driving unit to supply a higher driving power to the gate electrode of the switch device for a predetermined period of time starting at the start-up of the load than that in a steady state.Type: GrantFiled: June 5, 2013Date of Patent: July 15, 2014Assignee: Panasonic CorporationInventors: Kiyoshi Gotou, Masanori Hayashi, Takashi Kishida, Kouji Yamato
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Publication number: 20140012527Abstract: The present invention makes it possible to determine whether a mechanical component can be reused, without consulting a specialist, by: attaching to the mechanical component an IC tag that records identification information that includes at least one among the type, manufacturing time, manufacturing lot, and manufacturing history of the mechanical component, and that enables the identification information to be externally read by an electromagnetic method; recording, in the memory unit of an inspection device that can read the IC tag, inspection items corresponding to the identification information and the evaluation criteria of the inspection items; displaying an inspection item corresponding to the mechanical component on a display unit; obtaining result information from an input unit; and comparing the result information to the evaluation criteria and displaying, on the display unit, whether the part can be reused.Type: ApplicationFiled: March 19, 2012Publication date: January 9, 2014Inventors: Naota Yamamoto, Takashi Ito, Takashi Kishida, Yoriko Kosaka
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Publication number: 20130265096Abstract: A load control device includes a switching unit which is connected to a power source and a load in series and has a switch device having a transistor structure, a control unit configured to control start-up and stop of the load, and a gate driving unit, which is electrically insulated from the control unit and outputs a gate driving signal to the gate electrode of the switch device. The control unit controls the gate driving unit to supply a higher driving power to the gate electrode of the switch device for a predetermined period of time starting at the start-up of the load than that in a steady state.Type: ApplicationFiled: June 5, 2013Publication date: October 10, 2013Inventors: Kiyoshi GOTOU, Masanori HAYASHI, Takashi KISHIDA, Kouji YAMATO
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Patent number: 6847435Abstract: A laser distance measuring apparatus, for measuring the distance between objects existing in two directions at least as seen from the apparatus by using laser light, comprises two projectors for projecting laser beams along a specified projection axis toward each one of the objects, a photo detector for receiving reflected light of projection from each object, a distance measurement processor for measuring the distance from a reference point of the apparatus to each object on the basis of the reception signal to the projection by the photo detector, and a distance calculation processor for calculating the distance between the objects on the basis of the distance data measured by the distance measurement processor and the angle formed by two projection axes, in which the projection axis by one projector is variable in angle with respect to the other projector. Therefore, the distance between objects can be measured easily and at high precision by one distance measuring operation only.Type: GrantFiled: June 24, 2003Date of Patent: January 25, 2005Assignee: Matsushita Electric Works, Ltd.Inventors: Tatsuya Honda, Hiroshi Maeda, Takashi Kishida, Kazunari Yoshimura, Kazufumi Oogi, Hideshi Hamaguchi, Yoshimitsu Nakamura, Kuninori Nakamura
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Publication number: 20040051860Abstract: A laser distance measuring apparatus, for measuring the distance between objects existing in two directions at least as seen from the apparatus by using laser light, comprises two projectors for projecting laser beams along a specified projection axis toward each one of the objects, a photo detector for receiving reflected light of projection from each object, a distance measurement processor for measuring the distance from a reference point of the apparatus to each object on the basis of the reception signal to the projection by the photo detector, and a distance calculation processor for calculating the distance between the objects on the basis of the distance data measured by the distance measurement processor and the angle formed by two projection axes, in which the projection axis by one projector is variable in angle with respect to the other projector. Therefore, the distance between objects can be measured easily and at high precision by one distance measuring operation only.Type: ApplicationFiled: June 24, 2003Publication date: March 18, 2004Applicant: Matsushita Electric Works, Ltd.Inventors: Tatsuya Honda, Hiroshi Maeda, Takashi Kishida, Kazunari Yoshimura, Kazufumi Oogi, Hideshi Hamaguchi, Yoshimitsu Nakamura, Kuninori Nakamura
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Patent number: 6580126Abstract: A solid state relay composed of a series connected pair of LDMOSFETs has a minimized output capacitance. Each LDMOSFET is configured to have a silicon layer of a first conductive type, a drain region of the first conductive type diffused in the top surface of the silicon layer, a well region of a second conductive type diffused in the silicon layer in a laterally spaced relation from the drain region, and a source region of the first conductive type diffused within the well region to define a channel extending between the source region and a confronting edge of the well region along the top surface of the silicon layer. Each LDMOSFET is of an SOI (Silicon-On-Insulator) structure composed of a silicon substrate placed on a supporting plate, a buried oxide layer on the silicon substrate, and the silicon layer on the buried oxide layer.Type: GrantFiled: November 13, 2000Date of Patent: June 17, 2003Assignee: Matsushita Electric Works, Ltd.Inventors: Masahiko Suzumura, Hitomichi Takano, Yuji Suzuki, Takashi Kishida, Yoshiki Hayasaki, Yoshifumi Shirai, Takeshi Yoshida, Yasunori Miyamoto
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Patent number: 6448620Abstract: To provide a semiconductor device having a large allowable current, a demanded withstand voltage, and small output capacitance and resistance, the semiconductor device comprises a semiconductor layer formed on a semiconductor substrate, and the semiconductor layer includes a first conductivity type-drain region, a second conductivity type-well region apart from the drain region, a first conductivity type-source region in the well region apart from one end of the well region on the side of the drain region, a first conductivity type-drift region formed between one end of the well region and the drain region and in contact with the well region and the drain region, respectively, and a gate electrode formed spaced a gate oxide layer and on the well region located between the drift region and the source region; and the impurity concentration of the drift region decreases in the lateral direction and also in the vertical direction, respectively, as the distance from the drain region increases.Type: GrantFiled: December 22, 2000Date of Patent: September 10, 2002Assignee: Matsushita Electric Works, Ltd.Inventors: Yoshiki Hayasaki, Hitomichi Takano, Masahiko Suzumura, Yuji Suzuki, Yoshifumi Shirai, Takashi Kishida, Takeshi Yoshida, Takaaki Yoshihara
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Patent number: 6373101Abstract: A solid state relay composed of a series connected pair of LDMOSFETs has a minimized output capacitance. Each LDMOSFET is configured to have a silicon layer of a first conductive type, a drain region of the first conductive type diffused in the top surface of the silicon layer, a well region of a second conductive type diffused in the silicon layer in a laterally spaced relation from the drain region, and a source region of the first conductive type diffused within the well region to define a channel extending between the source region and a confronting edge of the well region along the top surface of the silicon layer. Each LDMOSFET is of an SOI (Silicon-On-Insulator) structure composed of a silicon substrate placed on a supporting plate, a buried oxide layer on the silicon substrate, and the silicon layer on the buried oxide layer.Type: GrantFiled: November 13, 2000Date of Patent: April 16, 2002Assignee: Matsushita Electric WorksInventors: Masahiko Suzumura, Hitomichi Takano, Yuji Suzuki, Takashi Kishida, Yoshiki Hayasaki, Yoshifumi Shirai, Takeshi Yoshida, Yasunori Miyamoto
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Publication number: 20010013624Abstract: To provide a semiconductor device having a large allowable current, a demanded withstand voltage, and small output capacitance and resistance, the semiconductor device comprises a semiconductor layer formed on a semiconductor substrate, and the semiconductor layer includes a first conductivity type-drain region, a second conductivity type-well region apart from the drain region, a first conductivity type-source region in the well region apart from one end of the well region on the side of the drain region, a first conductivity type-drift region formed between one end of the well region and the drain region and in contact with the well region and the drain region, respectively, and a gate electrode formed spaced a gate oxide layer and on the well region located between the drift region and the source region; and the impurity concentration of the drift region decreases in the lateral direction and also in the vertical direction, respectively, as the distance from the drain region increases.Type: ApplicationFiled: December 22, 2000Publication date: August 16, 2001Applicant: Matsushita Electric Works, Ltd.Inventors: Yoshiki Hayasaki, Hitomichi Takano, Masahiko Suzumura, Yuji Suzuki, Yoshifumi Shirai, Takashi Kishida, Takeshi Yoshida, Takaaki Yoshihara
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Patent number: 6211551Abstract: A solid state relay composed of a series connected pair of LDMOSFETs has a minimized output capacitance. Each LDMOSFET is configured to have a silicon layer of a first conductive type, a drain region of the first conductive type diffused in the top surface of the silicon layer, a well region of a second conductive type diffused in the silicon layer in a laterally spaced relation from the drain region, and a source region of the first conductive type diffused within the well region to define a channel extending between the source region and a confronting edge of the well region along the top surface of the silicon layer. Each LDMOSFET is of an SOI (Silicon-On-Insulator) structure composed of a silicon substrate placed on a supporting plate, a buried oxide layer on the silicon substrate, and the silicon layer on the buried oxide layer.Type: GrantFiled: June 26, 1998Date of Patent: April 3, 2001Assignee: Matsushita Electric Works, Ltd.Inventors: Masahiko Suzumura, Hitomichi Takano, Yuji Suzuki, Takashi Kishida, Yoshiki Hayasaki, Yoshifumi Shirai, Takeshi Yoshida, Yasunori Miyamoto
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Patent number: 5780900Abstract: A thin film transistor of SOI (Silicon-On-Insulator) type includes a buried oxide layer formed on a semiconductor substrate, a silicon layer of a first conductive type formed on the buried oxide layer, and an upper oxide layer formed on the silicon layer. The silicon layer has a body region of a second conductive type, source region of the first conductive type, drain region of the first conductive type, and a drift region of the first conductive type. The silicon layer is formed with a first portion of a thickness T1 in which the doping region is formed, and a second portion of a thickness T2 in which the body region is formed to reach the buried oxide layer. When the thicknesses T1 and T2 are determined so as to satisfy the relationships:0.4 .mu.m<T1,0.4 .mu.m.ltoreq.T2.ltoreq.1.5 .mu.m, andT2<T1,The transistor exhibits an improved power dissipation, high breakdown voltage, and a low on-resistance, and also provides advantages in a manufacturing process of the transistor.Type: GrantFiled: October 17, 1996Date of Patent: July 14, 1998Assignee: Matsushita Electric Works, Inc.Inventors: Yuji Suzuki, Hitomichi Takano, Masahiko Suzumura, Yoshiki Hayasaki, Takashi Kishida, Yoshifumi Shirai
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Patent number: 5053201Abstract: A process and apparatus for the preparation of a polyester, wherein a thin film polymerization apparatus having at least one columnar or cylindrical roller-shaped stirring vane rotating along and in close proximity to a substantially cylindrical vertical tank wall is used, and the stirring vane is caused to make an epicyclic movement along the tank wall in the circumferential direction thereof so that the direction of rotation is the same as the direction of revolution and a polyester-forming monomer and/or an oligomer thereof is dropped on the surface of the tank wall in the form of a thin film.Type: GrantFiled: September 5, 1986Date of Patent: October 1, 1991Assignee: Teijin LimitedInventors: Shinichi Yamauchi, Katsushi Sasaki, Eiji Matsumura, Yasuhiko Saito, Takashi Kishida
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Patent number: 4351492Abstract: Polyester yarns spun from spinnerets are delivered to bobbins held on a bobbin holder in a winding apparatus through godet rollers which have mirror finished surfaces and axially grooved surfaces. Upon threading the yarns on the bobbins, the yarns are moved to the axially grooved surface from the mirror finished surfaces by means of a yarn displacing guide disposed upstream of the uppermost godet roller. The change in the tension in the yarn caused by the threading operation of the yarn is transmitted beyond the godet rollers, and entanglement of the yarn around the godet roller does not occur.Type: GrantFiled: November 2, 1979Date of Patent: September 28, 1982Assignee: Teijin LimitedInventors: Hideki Aoyama, Takashi Kishida
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Patent number: 3971517Abstract: A guide roller is traversed substantially in parallel to the axis of an uprightly supported bobbin at a speed slow enough not to form appreciable twilled angles of a wound yarn. The yarn continuously extruded from a spinning apparatus at a speed higher than 2000 m/min is introduced substantially in parallel to the axis of the bobbin and changes its direction to right angles with respect to the axis of the bobbin while travelling through the guide roller. The guide roller traverses with shorter traverse strokes as the diameter of the wound yarn becomes larger.Type: GrantFiled: August 12, 1974Date of Patent: July 27, 1976Assignee: Teijin LimitedInventors: Yosio Matuura, Shoichi Murakami, Norihisa Yamaguchi, Takashi Kishida, Sadao Kadokura, Kiyoshi Imai