Abstract: A control device for a lock-up clutch includes a control unit, an abnormality determination unit, a release control unit and a prohibition unit. The control unit is configured to control an engagement state of a lock-up clutch, and to perform a slip lock-up control by performing a feedback control of an engagement hydraulic pressure to be a first slip amount during coasting. The abnormality determination unit is configured to determine an abnormality when a state continues with a slip amount being equal to or greater than a second slip amount. The release control unit is configured to release the lock-up clutch when the abnormality is determined. The prohibition unit is configured to allow the control unit to raise the engagement hydraulic pressure by a prescribed pressure, and to prohibit determination by the abnormality determination unit, when the transmission ratio is downshifted during coasting while the slip lock-up control is performed.

Abstract: A vehicle has an engine (1) as a driving source. Output rotation of the engine (1) is transmitted to driving wheels (7) through a torque converter (2) equipped with a lock-up clutch, a first gear train (3), a transmission (4) formed by combination of a variator (20) and an auxiliary transmission (30), a second gear train (5) and a final speed reduction device (6). The second gear train (5) is provided with a parking mechanism (8) that mechanically locks an output shaft of the transmission (4) so that the output shaft of the transmission (4) cannot rotate during parking of the vehicle. A shift speed when down-shift is performed by the variator (20) during a torque-down request to the engine (1) is set to be slower than a shift speed when down-shift is performed by the variator (20) during a non-torque-down request.

Abstract: A vehicle has an engine (1) as a driving source. Output rotation of the engine (1) is transmitted to driving wheels (7) through a torque converter (2) equipped with a lock-up clutch, a first gear train (3), a transmission (4) formed by combination of a variator (20) and an auxiliary transmission (30), a second gear train (5) and a final speed reduction device (6). The second gear train (5) is provided with a parking mechanism (8) that mechanically locks an output shaft of the transmission (4) so that the output shaft of the transmission (4) cannot rotate during parking of the vehicle. A shift speed when down-shift is performed by the variator (20) during a torque-down request to the engine (1) is set to be slower than a shift speed when down-shift is performed by the variator (20) during a non-torque-down request.

Abstract: As a mode switching shift line when a sub-transmission mechanism is switched from a first-speed to a second-speed, a first mode switching shift line, which prioritizes a learning of a hydraulic pressure with which a Low brake starts to slip and a learning of a hydraulic pressure with which a High clutch starts to transmit a torque, or a second mode switching shift line, which is a shift line in a Low side with respect to the first mode switching shift line and prioritizes a fuel efficiency of an engine is selected, and the sub-transmission mechanism is switched from the first-speed to the second-speed on the basis of the selected mode switching shift line.

Abstract: A control device for a lock-up clutch includes a control unit, an abnormality determination unit, a release control unit and a prohibition unit. The control unit is configured to control an engagement state of a lock-up clutch, and to perform a slip lock-up control by performing a feedback control of an engagement hydraulic pressure to be a first slip amount during coasting. The abnormality determination unit is configured to determine an abnormality when a state continues with a slip amount being equal to or greater than a second slip amount. The release control unit is configured to release the lock-up clutch when the abnormality is determined. The prohibition unit is configured to allow the control unit to raise the engagement hydraulic pressure by a prescribed pressure, and to prohibit determination by the abnormality determination unit, when the transmission ratio is downshifted during coasting while the slip lock-up control is performed.

Abstract: An automatic transmission control device implements a downshift by disengagement of a clutch that is engaged in a gear position before the downshift. It is determined whether an engine state is in a predetermined region in which a change of an engine torque per a change of an accelerator pedal opening is smaller than that in another region, and the engine torque is within a predetermined range, and an engine rotational speed is within a predetermined range. It is determined whether an operating state is in a predetermined state of accelerator operation in which the accelerator pedal opening is larger than a predetermined value, and an accelerator pedal opening change rate has an absolute value smaller than a predetermined value. The downshift is inhibited in response to determination that the engine state is in the predetermined region and the operating state is in the predetermined state of accelerator operation.

Abstract: As a mode switching shift line when a sub-transmission mechanism is switched from a first-speed to a second-speed, a first mode switching shift line, which prioritizes a learning of a hydraulic pressure with which a Low brake starts to slip and a learning of a hydraulic pressure with which a High clutch starts to transmit a torque, or a second mode switching shift line, which is a shift line in a Low side with respect to the first mode switching shift line and prioritizes a fuel efficiency of an engine is selected, and the sub-transmission mechanism is switched from the first-speed to the second-speed on the basis of the selected mode switching shift line.

Abstract: An automatic transmission control device implements a downshift by disengagement of a clutch that is engaged in a gear position before the downshift. It is determined whether an engine state is in a predetermined region in which a change of an engine torque per a change of an accelerator pedal opening is smaller than that in another region, and the engine torque is within a predetermined range, and an engine rotational speed is within a predetermined range. It is determined whether an operating state is in a predetermined state of accelerator operation in which the accelerator pedal opening is larger than a predetermined value, and an accelerator pedal opening change rate has an absolute value smaller than a predetermined value. The downshift is inhibited in response to determination that the engine state is in the predetermined region and the operating state is in the predetermined state of accelerator operation.

Abstract: Engine output control apparatus has shift range detecting section detecting shift range of automatic transmission; vehicle speed detecting section detecting vehicle speed; engine output state detecting section detecting engine output state; and controller. The controller performs (a) judgment control judging that torque converter is in a stall state if following judgment conditions (i) to (iii) are satisfied, (i) shift range is drive range, (ii) vehicle speed is equal to or less than predetermined vehicle speed, (iii) engine is in a high output state, (b) cumulation control cumulating a period of agreement of the judgment conditions if the judgment conditions are satisfied, and (c) output suppression control suppressing output of the engine if a control start condition is satisfied by cumulation of the agreement period. The control start condition is set so that as the vehicle speed becomes higher, start of the output suppression control is more delayed.

Abstract: Engine output control apparatus has shift range detecting section detecting shift range of automatic transmission; vehicle speed detecting section detecting vehicle speed; engine output state detecting section detecting engine output state; and controller. The controller performs (a) judgment control judging that torque converter is in a stall state if following judgment conditions (i) to (iii) are satisfied, (i) shift range is drive range, (ii) vehicle speed is equal to or less than predetermined vehicle speed, (iii) engine is in a high output state, (b) cumulation control cumulating a period of agreement of the judgment conditions if the judgment conditions are satisfied, and (c) output suppression control suppressing output of the engine if a control start condition is satisfied by cumulation of the agreement period. The control start condition is set so that as the vehicle speed becomes higher, start of the output suppression control is more delayed.

Abstract: A soft error correction method is for a memory system having memory access controllers accessing memories for storing byte-sliced data in cycle synchronism, and a system controller receiving a memory access from an arbitrary one of MPUs and issuing a memory address to the memory access controllers. When a correctable error is detected in data read from one memory, an error address where the error was detected is held within a memory access controller, and an error notification is made to the system controller from the memory access controller. In response to the error notification, the memory access controller holds the error address from the system controller without intervention from the MPUs, and reads, corrects and rewrites the data to the error address.

Abstract: A clock supply method for supplying a clock to a plurality of processing units includes supplying a clock from a first clock supply unit to processing units forming a first group as a primary clock and to processing units forming a second group as a standby clock; supplying a clock from a second clock supply unit including a clock source different from that of the first clock supply unit to the processing units forming the second group as a primary clock and to the processing units forming the first group as a standby clock; and when a processing unit in the first or second group detects an abnormality of the primary clock, switching the standby clock into use in place of the primary clock being supplied to the processing units that has detected the abnormality belongs; wherein the first and second clock supply units supply clocks with the same frequency.

Abstract: According to an aspect of an embodiment, a memory controller for writing data into and reading data from a memory, comprises an error detector for detecting an error of data stored in the memory when reading the data, a time stamper for generating first time information indicative of the time when data is written into the memory, the first time information being written together with the data into an address location of the memory where the error has been detected, a timer for measuring a time period from the time indicated by the first time information until the time of subsequent occurrence of an error of data stored in said address location and a counter for counting a number of accesses to the address location over the time period.

Abstract: A clock supply method for supplying a clock to a plurality of processing units includes supplying a clock from a first clock supply unit to processing units forming a first group as a primary clock and to processing units forming a second group as a standby clock; supplying a clock from a second clock supply unit including a clock source different from that of the first clock supply unit to the processing units forming the second group as a primary clock and to the processing units forming the first group as a standby clock; and when a processing unit in the first or second group detects an abnormality of the primary clock, switching the standby clock into use in place of the primary clock being supplied to the processing units that has detected the abnormality belongs; wherein the first and second clock supply units supply clocks with the same frequency.

Abstract: A soft error correction method is for a memory system having memory access controllers accessing memories for storing byte-sliced data in cycle synchronism, and a system controller receiving a memory access from an arbitrary one of MPUs and issuing a memory address to the memory access controllers. When a correctable error is detected in data read from one memory, an error address where the error was detected is held within a memory access controller, and an error notification is made to the system controller from the memory access controller. In response to the error notification, the memory access controller holds the error address from the system controller without intervention from the MPUs, and reads, corrects and rewrites the data to the error address.

Abstract: A soft error correction method is for a memory system having memory access controllers accessing memories for storing byte-sliced data in cycle synchronism, and a system controller receiving a memory access from an arbitrary one of MPUs and issuing a memory address to the memory access controllers. When a correctable error is detected in data read from one memory, an error address where the error was detected is held within a memory access controller, and an error notification is made to the system controller from the memory access controller. In response to the error notification, the memory access controller holds the error address from the system controller without intervention from the MPUs, and reads, corrects and rewrites the data to the error address.

Abstract: A computer system includes a plurality of system boards each of which includes two systems arranged in a duplicated structure and a data relay device. The data relay device includes a degeneration determining unit that determines whether each of the systems is degenerated based on a signal that is transmitted from the each of the systems; a dummy-information creating unit that creates dummy information by adding dummy data to identification information and destination information, the identification information indicating a head of proper data that is transmitted from one of the systems constituting the duplicated structure with the other system that has been determined as being degenerated, and the destination information indicating destination of the data; and a data transmitting unit that transmits, as synchronized data, proper information that is transmitted from the one of the systems, and the dummy information.

Abstract: The present invention provides a control method for an error detection & correction apparatus, comprising a plurality of data processing apparatuses which reside in a data communications path and partake in exchanging data by the unit of error correcting code, and a plurality of information exchange paths which are installed between the plurality of data processing apparatuses; and generating a true syndrome by exchanging a partial syndrome relating to a part of the data partaken by each of the data processing apparatuses by way of the information exchange paths, comprising the step of exchanging renewal information relating to a part of the data partaken by each of the data processing apparatuses with the other data processing apparatus by way of the information exchange path.

Abstract: According to an aspect of an embodiment, a memory controller for writing data into and reading data from a memory, comprises an error detector for detecting an error of data stored in the memory when reading the data, a time stamper for generating first time information indicative of the time when data is written into the memory, the first time information being written together with the data into an address location of the memory where the error has been detected, a timer for measuring a time period from the time indicated by the first time information until the time of subsequent occurrence of an error of data stored in said address location and a counter for counting a number of accesses to the address location over the time period.

Abstract: A soft error correction method is for a memory system having memory access controllers accessing memories for storing byte-sliced data in cycle synchronism, and a system controller receiving a memory access from an arbitrary one of MPUs and issuing a memory address to the memory access controllers. When a correctable error is detected in data read from one memory, an error address where the error was detected is held within a memory access controller, and an error notification is made to the system controller from the memory access controller. In response to the error notification, the memory access controller holds the error address from the system controller without intervention from the MPUs, and reads, corrects and rewrites the data to the error address.