Abstract: A thermal analysis apparatus includes: a cylindrical heating furnace extending in an axial direction; a weight detector arranged on a rear-end side in the axial direction of the cylindrical heating furnace and including levers extending in the axial direction to detect a weight; a connecting portion for connecting the cylindrical heating furnace and the weight detector to communicate an internal space of the cylindrical heating furnace with an internal space of the weight detector and positioning the levers from the weight detector into the cylindrical heating furnace; sample holding portions connected to tip ends of the levers and arranged inside the cylindrical heating furnace and holding a sample; resistance heaters arranged to cover the weight detector and energized by an electric current of 6 A or less; and a heater control part for controlling an energization state of the resistance heaters to maintain the weight detector at a constant temperature.

Abstract: A thermal analysis apparatus includes: a cylindrical heating furnace extending in an axial direction; a weight detector arranged on a rear-end side in the axial direction of the cylindrical heating furnace and including levers extending in the axial direction to detect a weight; a connecting portion for connecting the cylindrical heating furnace and the weight detector to communicate an internal space of the cylindrical heating furnace with an internal space of the weight detector and positioning the levers from the weight detector into the cylindrical heating furnace; sample holding portions connected to tip ends of the levers and arranged inside the cylindrical heating furnace and holding a sample; resistance heaters arranged to cover the weight detector and energized by an electric current of 6 A or less; and a heater control part for controlling an energization state of the resistance heaters to maintain the weight detector at a constant temperature.

Abstract: A flip flop device, a semiconductor integrated circuit, and a method and apparatus for designing a semiconductor integrated circuit that prevents timing violations while preventing the circuit scale from increasing. A flip flop including first, second, and third latch circuits is stored as a standard cell in a cell library of a designing apparatus. The output of the second latch circuit becomes a first output signal of the flip flop. The second latch circuit provides the third latch circuit with a signal generated by latching a data signal with a clock signal. An output of the third latch circuit becomes a second output signal of the flip flop. When an error path having the possibility of a hold time violation is found, output of the flip flop in a former stage is changed from the first output to the second output in the error path.

Abstract: A flip flop device, a semiconductor integrated circuit, and a method and apparatus for designing a semiconductor integrated circuit that prevents timing violations while preventing the circuit scale from increasing. A flip flop including first, second, and third latch circuits is stored as a standard cell in a cell library of a designing apparatus. The output of the second latch circuit becomes a first output signal of the flip flop. The second latch circuit provides the third latch circuit with a signal generated by latching a data signal with a clock signal. An output of the third latch circuit becomes a second output signal of the flip flop. When an error path having the possibility of a hold time violation is found, output of the flip flop in a former stage is changed from the first output to the second output in the error path.

Abstract: A digital-to-analog conversion circuit including a plurality of unit current output cells (1) arranged in a matrix. Each of the current output cells (1) includes a unit current source (11) having a power supply input and a current output, and a selecting switch (12) connected to the current output and having two switching output terminals. The circuit further includes at least one ½ and/or ¼ weighted current output cell (2) disposed on a row in the matrix, and at least one ½ and/or ¼ supplementary current source (8) disposed on a desired row so that the total current consumption of the unit, weighted and supplementary current sources on each row is substantially the same. A decoder responds to a digital signal to control the switching of the selecting switches one by one as the digital signal gradually increases.