Patents by Inventor Takashi Kuraishi

Takashi Kuraishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8400806
    Abstract: A technology that makes it possible to reduce fluctuation in operating voltage for operating the circuits formed in the core region of a semiconductor device is provided. This semiconductor device is so arranged that the core region is divided into multiple functional blocks and power can be supplied and this power supply can be interrupted with respect to each of the divided functional blocks. The core region formed in the semiconductor chip is divided into multiple functional blocks. A power switch row in which multiple power switches are arranged is disposed in the boundaries between the divided functional blocks. These power switches have a function of controlling the supply of reference potential to each of functional blocks and the interruption of this supply. A feature of the invention is that reference pads are disposed directly above the power switch rows. This shortens the wires coupling together the reference pads and the power switches.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: March 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Toshio Sasaki, Yoshihiko Yasu, Takashi Kuraishi, Ryo Mori
  • Publication number: 20110085400
    Abstract: A technology that makes it possible to reduce fluctuation in operating voltage for operating the circuits formed in the core region of a semiconductor device is provided. This semiconductor device is so arranged that the core region is divided into multiple functional blocks and power can be supplied and this power supply can be interrupted with respect to each of the divided functional blocks. The core region formed in the semiconductor chip is divided into multiple functional blocks. A power switch row in which multiple power switches are arranged is disposed in the boundaries between the divided functional blocks. These power switches have a function of controlling the supply of reference potential to each of functional blocks and the interruption of this supply. A feature of the invention is that reference pads are disposed directly above the power switch rows. This shortens the wires coupling together the reference pads and the power switches.
    Type: Application
    Filed: December 17, 2010
    Publication date: April 14, 2011
    Inventors: TOSHIO SASAKI, Yoshihiko Yasu, Takashi Kuraishi, Ryo Mori
  • Publication number: 20110068826
    Abstract: A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed.
    Type: Application
    Filed: December 1, 2010
    Publication date: March 24, 2011
    Inventors: Yuri AZUMA, Yoshihiko Yasu, Yasuto Igarashi, Takashi Kuraishi, Kazumasa Yanagisawa
  • Patent number: 7872891
    Abstract: A technology that makes it possible to reduce fluctuation in operating voltage for operating the circuits formed in the core region of a semiconductor device is provided. This semiconductor device is so arranged that the core region is divided into multiple functional blocks and power can be supplied and this power supply can be interrupted with respect to each of the divided functional blocks. The core region formed in the semiconductor chip is divided into multiple functional blocks. A power switch row in which multiple power switches are arranged is disposed in the boundaries between the divided functional blocks. These power switches have a function of controlling the supply of reference potential to each of functional blocks and the interruption of this supply. A feature of the invention is that reference pads are disposed directly above the power switch rows. This shortens the wires coupling together the reference pads and the power switches.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: January 18, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Toshio Sasaki, Yoshihiko Yasu, Takashi Kuraishi, Ryo Mori
  • Patent number: 7855593
    Abstract: A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: December 21, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Yuri Azuma, Yoshihiko Yasu, Yasuto Igarashi, Takashi Kuraishi, Kazumasa Yanagisawa
  • Patent number: 7714606
    Abstract: A plurality of MOS transistors each having an SOI structure includes, in mixed form, those brought into body floating and whose body voltages are fixed and variably set. When a high-speed operation is expected in a logic circuit in which operating power is relatively a low voltage and a switching operation is principally performed, body floating may be adopted. Body voltage fixing may be adopted in an analog system circuit that essentially dislikes a kink phenomenon of a current-voltage characteristic. Body bias variable control may be adopted in a logic circuit that requires the speedup of operation in an active state and needs low power consumption in a standby state. Providing in mixed form the transistors which are subjected to the body floating and the body voltage fixing and which are variably controlled in body voltage, makes it easier to adopt an accurate body bias according to a circuit function and a circuit configuration in terms of the speedup of operation and the low power consumption.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: May 11, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Osamu Ozawa, Toshio Sasaki, Ryo Mori, Takashi Kuraishi, Yoshihiko Yasu
  • Publication number: 20100090282
    Abstract: The semiconductor integrated circuit has so-called SOI type first MOS transistors (MNtk, MPtk) and second MOS transistors (MNtn, MPtn). The first MOS transistors have a gate isolation film thicker than that the second MOS transistors have. The first and second MOS transistors constitute a power-supply-interruptible circuit (6) and a power-supply-uninterrupted circuit (7). The power-supply-interruptible circuit has the first MOS transistors each constituting a power switch (10) between a source line (VDD) and a ground line (VSS), and the second MOS transistors connected in series with the power switch. A gate control signal for the first MOS transistors each constituting a power switch is made larger in amplitude than that for the second MOS transistors. This enables power-source cutoff control with a high degree of flexibility commensurate with the device isolation structure, which an SOI type semiconductor integrated circuit has originally.
    Type: Application
    Filed: December 17, 2009
    Publication date: April 15, 2010
    Inventors: OSAMU OZAWA, Toshio Sasaki, Ryo Mori, Takashi Kuraishi, Yoshihiko Yasu, Koichiro Ishibashi
  • Publication number: 20100034044
    Abstract: A technology that makes it possible to reduce fluctuation in operating voltage for operating the circuits formed in the core region of a semiconductor device is provided. This semiconductor device is so arranged that the core region is divided into multiple functional blocks and power can be supplied and this power supply can be interrupted with respect to each of the divided functional blocks. The core region formed in the semiconductor chip is divided into multiple functional blocks. A power switch row in which multiple power switches are arranged is disposed in the boundaries between the divided functional blocks. These power switches have a function of controlling the supply of reference potential to each of functional blocks and the interruption of this supply. A feature of the invention is that reference pads are disposed directly above the power switch rows. This shortens the wires coupling together the reference pads and the power switches.
    Type: Application
    Filed: October 16, 2009
    Publication date: February 11, 2010
    Inventors: TOSHIO SASAKI, Yoshihiko YASU, Takashi KURAISHI, Ryo MORI
  • Patent number: 7652333
    Abstract: The semiconductor integrated circuit has so-called SOI type first MOS transistors (MNtk, MPtk) and second MOS transistors (MNtn, MPtn). The first MOS transistors have a gate isolation film thicker than that the second MOS transistors have. The first and second MOS transistors constitute a power-supply-interruptible circuit (6) and a power-supply-uninterrupted circuit (7). The power-supply-interruptible circuit has the first MOS transistors each constituting a power switch (10) between a source line (VDD) and a ground line (VSS), and the second MOS transistors connected in series with the power switch. A gate control signal for the first MOS transistors each constituting a power switch is made larger in amplitude than that for the second MOS transistors. This enables power-source cutoff control with a high degree of flexibility commensurate with the device isolation structure, which an SOI type semiconductor integrated circuit has originally.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: January 26, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Osamu Ozawa, Toshio Sasaki, Ryo Mori, Takashi Kuraishi, Yoshihiko Yasu, Koichiro Ishibashi
  • Patent number: 7623364
    Abstract: A technology that makes it possible to reduce fluctuation in operating voltage for operating the circuits formed in the core region of a semiconductor device is provided. This semiconductor device is so arranged that the core region is divided into multiple functional blocks and power can be supplied and this power supply can be interrupted with respect to each of the divided functional blocks. The core region formed in the semiconductor chip is divided into multiple functional blocks. A power switch row in which multiple power switches are arranged is disposed in the boundaries between the divided functional blocks. These power switches have a function of controlling the supply of reference potential to each of functional blocks and the interruption of this supply. A feature of the invention is that reference pads are disposed directly above the power switch rows. This shortens the wires coupling together the reference pads and the power switches.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: November 24, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Toshio Sasaki, Yoshihiko Yasu, Takashi Kuraishi, Ryo Mori
  • Patent number: 7612604
    Abstract: A body bias control system allows for independent design of a functional module, thereby reducing the burden of designing the module. The body bias control system provides a switch circuit having an area in which the body bias is controlled independently of its outside portion, for controlling the supply of body bias in the vicinity of the area. Preferably three types of switches are provided for switching the body bias to suitable levels for a standby mode, a mode of normal operation and a mode of high-speed operation.
    Type: Grant
    Filed: May 6, 2003
    Date of Patent: November 3, 2009
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Masayuki Miyazaki, Yusuke Kanno, Goichi Ono, Toshinobu Shinbo, Yoshihiko Yasu, Kazumasa Yanagisawa, Takashi Kuraishi
  • Publication number: 20090267686
    Abstract: A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed.
    Type: Application
    Filed: July 6, 2009
    Publication date: October 29, 2009
    Inventors: Yuri Azuma, Yoshihiko Yasu, Yasuto Igarashi, Takashi Kuraishi, Kazumasa Yanagisawa
  • Publication number: 20090169063
    Abstract: A fingerprinting technique of taking a left fingerprint, storing the taken fingerprint, and physically recording/storing information collected when the fingerprint is taken so as to add a physical evidence adoption capability. Fingerprinting means comprises a fingerprinting section (11) adapted for taking a fingerprint and composed of an adhesive layer or a layer (111) made of a substance to which ridges of a fingerprint can be transferred and a data recording section (12) provided in association with the fingerprinting section (11) and adapted for recording various information on the person having the fingerprint. The fingerprinting section (11) and the data recording section (12) are provided on the same base (1) and the covered with a protective film (13).
    Type: Application
    Filed: October 12, 2005
    Publication date: July 2, 2009
    Inventor: Takashi Kuraishi
  • Publication number: 20080239780
    Abstract: A technology that makes it possible to reduce fluctuation in operating voltage for operating the circuits formed in the core region of a semiconductor device is provided. This semiconductor device is so arranged that the core region is divided into multiple functional blocks and power can be supplied and this power supply can be interrupted with respect to each of the divided functional blocks. The core region formed in the semiconductor chip is divided into multiple functional blocks. A power switch row in which multiple power switches are arranged is disposed in the boundaries between the divided functional blocks. These power switches have a function of controlling the supply of reference potential to each of functional blocks and the interruption of this supply. A feature of the invention is that reference pads are disposed directly above the power switch rows. This shortens the wires coupling together the reference pads and the power switches.
    Type: Application
    Filed: January 17, 2008
    Publication date: October 2, 2008
    Inventors: Toshio SASAKI, Yoshihiko YASU, Takashi KURAISHI, Ryo MORI
  • Patent number: 7411267
    Abstract: The invention provides a semiconductor integrated circuit device with improved designing efficiency while achieving higher functions. An inner circuit is surrounded by a plurality of cells in which a first switch element for connecting a power supply voltage line or a ground voltage supply line to a power supply line of an internal circuit is disposed below power supply lines extending in a first and second directions, and the power lines are connected together.
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: August 12, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Kentaro Yamawaki, Yoshihiko Yasu, Yasuto Igarashi, Takashi Kuraishi, Kazumasa Yanagisawa
  • Publication number: 20070215952
    Abstract: The semiconductor integrated circuit has so-called SOI type first MOS transistors (MNtk, MPtk) and second MOS transistors (MNtn, MPtn). The first MOS transistors have a gate isolation film thicker than that the second MOS transistors have. The first and second MOS transistors constitute a power-supply-interruptible circuit (6) and a power-supply-uninterrupted circuit (7). The power-supply-interruptible circuit has the first MOS transistors each constituting a power switch (10) between a source line (VDD) and a ground line (VSS), and the second MOS transistors connected in series with the power switch. A gate control signal for the first MOS transistors each constituting a power switch is made larger in amplitude than that for the second MOS transistors. This enables power-source cutoff control with a high degree of flexibility commensurate with the device isolation structure, which an SOI type semiconductor integrated circuit has originally.
    Type: Application
    Filed: December 21, 2006
    Publication date: September 20, 2007
    Inventors: Osamu OZAWA, Toshio Sasaki, Ryo Mori, Takashi Kuraishi, Yoshihiko Yasu, Koichiro Ishibashi
  • Publication number: 20070176233
    Abstract: A plurality of MOS transistors each having an SOI structure includes, in mixed form, those brought into body floating and whose body voltages are fixed and variably set. When a high-speed operation is expected in a logic circuit in which operating power is relatively a low voltage and a switching operation is principally performed, body floating may be adopted. Body voltage fixing may be adopted in an analog system circuit that essentially dislikes a kink phenomenon of a current-voltage characteristic. Body bias variable control may be adopted in a logic circuit that requires the speedup of operation in an active state and needs low power consumption in a standby state. Providing in mixed form the transistors which are subjected to the body floating and the body voltage fixing and which are variably controlled in body voltage, makes it easier to adopt an accurate body bias according to a circuit function and a circuit configuration in terms of the speedup of operation and the low power consumption.
    Type: Application
    Filed: December 15, 2006
    Publication date: August 2, 2007
    Inventors: Osamu Ozawa, Toshio Sasaki, Ryo Mori, Takashi Kuraishi, Yoshihiko Yasu
  • Publication number: 20050232053
    Abstract: A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided.
    Type: Application
    Filed: April 20, 2005
    Publication date: October 20, 2005
    Inventors: Yuri Azuma, Yoshihiko Yasu, Yasuto Igarashi, Takashi Kuraishi, Kazumasa Yanagisawa
  • Publication number: 20050218959
    Abstract: The invention provides a semiconductor integrated circuit device with improved designing efficiency while achieving higher functions.
    Type: Application
    Filed: February 3, 2005
    Publication date: October 6, 2005
    Inventors: Kentaro Yamawaki, Yoshihiko Yasu, Yasuto Igarashi, Takashi Kuraishi, Kazumasa Yanagisawa
  • Publication number: 20040016977
    Abstract: A body bias control system allows for independent design of a functional module, thereby reducing the burden of designing the module. The body bias control system provides a switch circuit having an area in which the body bias is controlled independently of its outside portion, for controlling the supply of body bias in the vicinity of the area. Preferably three types of switches are provided for switching the body bias to suitable levels for a standby mode, a mode of normal operation and a mode of high-speed operation.
    Type: Application
    Filed: May 6, 2003
    Publication date: January 29, 2004
    Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Masayuki Miyazaki, Yusuke Kanno, Goichi Ono, Toshinobu Shinbo, Yoshihiko Yasu, Kazumasa Yanagisawa, Takashi Kuraishi