Abstract: A semiconductor storage device includes a first conductive layer that extends in a first direction; a second conductive layer that extends in the first direction and is arranged with the first conductive layer in a second direction; a first insulating layer that is provided between the first conductive layer and the second conductive layer; a semiconductor layer that extends in the second direction and faces the first conductive layer, the second conductive layer, and the first insulating layer in a third direction; a first charge storage layer that is provided between the first conductive layer and the semiconductor layer; a second charge storage layer that is provided between the second conductive layer and the semiconductor layer; a first high dielectric constant layer that is provided between the first conductive layer and the first charge storage layer; and a second high dielectric constant layer provided between the second conductive layer and the second charge storage layer.

Abstract: A semiconductor memory device includes a plurality of conductive layers, a semiconductor layer opposed to the plurality of conductive layers, and an electric charge accumulation portion disposed between the semiconductor layer and the plurality of conductive layers. The electric charge accumulation portion includes a plurality of first electric charge accumulation portions opposed to the plurality of conductive layers, and a plurality of second electric charge accumulation portions disposed in positions different from the plurality of first electric charge accumulation portions. A distance between the first electric charge accumulation portion and the semiconductor layer is smaller than a distance between the second electric charge accumulation portion and the semiconductor layer. A distance between the second electric charge accumulation portion and the conductive layers is smaller than a distance between the first electric charge accumulation portion and the conductive layers.

Abstract: A semiconductor memory device according to an embodiment includes a substrate, first and second conductive layers, and a first pillar. The first conductive layer is provided above the substrate and includes a first N-type semiconductor region and a first P-type semiconductor region. The second conductive layers are provided above the first conductive layer and stacked at intervals. The first pillar includes a first semiconductor layer and a first insulating layer. The first semiconductor layer is provided through the second conductive layers and is in contact with each of the first N-type semiconductor region and the first P-type semiconductor region. The first insulating layer is provided between the first semiconductor layer and the second conductive layers.

Abstract: A semiconductor memory device includes a substrate, a multi-layered structure including a plurality of insulating layers and a plurality of conductive layers that are alternately formed above the substrate, and a pillar extending through the multi-layered structure. The pillar includes a semiconductor body extending along the pillar, and a charge-storing film around the semiconductor body, the charge-storing film having a first thickness at first portions facing the insulating layers and a second thickness greater than the first thickness at second portions facing the conductive layers.

Abstract: A semiconductor memory device includes a substrate, a multi-layered structure including a plurality of insulating layers and a plurality of conductive layers that are alternately formed above the substrate, and a pillar extending through the multi-layered structure. The pillar includes a semiconductor body extending along the pillar, and a charge-storing film around the semiconductor body, the charge-storing film having a first thickness at first portions facing the insulating layers and a second thickness greater than the first thickness at second portions facing the conductive layers.

Abstract: An integrated circuit device according to an embodiment includes a semiconductor substrate, a first semiconductor member and a second semiconductor member provided on the semiconductor substrate, a first electrode disposed between the first semiconductor member and the second semiconductor member, and a second electrode disposed between the semiconductor substrate and the first electrode. The first semiconductor member and the second semiconductor member extend in a first direction perpendicular to an upper surface of the semiconductor substrate. The first semiconductor member and the second semiconductor member are separated in a second direction orthogonal to the first direction. The first electrode extends in a third direction intersecting both the first direction and the second direction. The second electrode extends in the third direction.

Abstract: According to an embodiment, a semiconductor device includes a plurality of wires provided on an insulating layer. Each of the wires includes one or more metal crystal grains. An average width of each of the wires and an average interval between the wires adjacent to each other are nearly equal to or less than a mean free path of free electrons in a bulk crystal of the metal. A specific crystal orientation in which size effect of electrical resistivity weakens due to anisotropy of Fermi velocity in the metal is substantially parallel to a current direction in at least a part of the crystal grains in each of the wires.

Abstract: According to an embodiment, a simulation method for resistance variations of a plurality of wires includes creating a numerical expression model for the resistance that is a function of parameters of a cross-sectional shape of the wire, based on the resistance calculated in a Monte Carlo Simulation, dividing each of the wires into a plurality of small elements in a length direction, calculating the resistance of each of the small elements by assigning the parameters of the cross-sectional shape characterizing the cross-sectional shape of each of the small elements to the numerical expression model, and calculating a sum of the resistances of the small elements in each of the wires.

Abstract: An integrated circuit device according to an embodiment includes a semiconductor substrate, a first semiconductor member and a second semiconductor member provided on the semiconductor substrate, a first electrode disposed between the first semiconductor member and the second semiconductor member, and a second electrode disposed between the semiconductor substrate and the first electrode. The first semiconductor member and the second semiconductor member extend in a first direction perpendicular to an upper surface of the semiconductor substrate. The first semiconductor member and the second semiconductor member are separated in a second direction orthogonal to the first direction. The first electrode extends in a third direction intersecting both the first direction and the second direction. The second electrode extends in the third direction.

Abstract: An integrated circuit device according to an embodiment, includes a semiconductor member, a first electrode and a second electrode. The semiconductor member includes a first portion of a first conductivity type, a second portion of a second conductivity type, and a third portion of the first conductivity type disposed in this order along a first direction. The first electrode is disposed on a second direction side as viewed from the semiconductor member. The second electrode is disposed on an opposite side of the second direction as viewed from the semiconductor member. An end portion of the second electrode on a first direction side is located in the first direction side rather than that of the first electrode. An end portion of the second electrode on an opposite side of the first direction is located in the first direction side rather than that of the first electrode.

Abstract: In one embodiment, a semiconductor device includes a substrate, and a plurality of interconnects provided in the same interconnect layer above the substrate. The device further includes a plurality of insulators provided so as to be buried between the plurality of interconnects. Moreover, the plurality of interconnects include an interconnect group in which 2N or more interconnects are successively arrayed so that correlation coefficients of line edge roughness (LER) between both side surfaces of the respective interconnects are positive, where N is an integer of 4 or more.

Abstract: In one embodiment, a semiconductor device includes a substrate, and a plurality of interconnects provided in the same interconnect layer above the substrate. The device further includes a plurality of insulators provided so as to be buried between the plurality of interconnects. Moreover, the plurality of interconnects include an interconnect group in which 2N or more interconnects are successively arrayed so that correlation coefficients of line edge roughness (LER) between both side surfaces of the respective interconnects are positive, where N is an integer of 4 or more.

Abstract: A Monte Carlo simulation method for simulating movement of a carrier by alternately repeating a scattering process and a drift process, includes calculating, as a scattering time, a relaxation time by a Drude's formula in the scattering process, and determining a state of a carrier after the scattering, on the basis of a distribution function of a thermal equilibrium state.

Abstract: A semiconductor device simulation apparatus includes a first module configured to compute a reciprocal of the momentum relaxation time with respect to a part which is processed as an anisotropic scattering process of a carrier, and to compute the free-flight time by using the reciprocal of the momentum relaxation time, a second module configured to compute a drift process of the carrier during the free-flight time, and a third module configured to compute a scattering process by regarding a scattering a after of the drift process as an isotropic scattering, and by an output of the second module.