Patents by Inventor Takashi Maegawa

Takashi Maegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10186517
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a first insulating film, a stacked body, and a first pillar. At least a portion of an upper layer portion of the substrate is conductive. The first insulating film is provided in a portion of the substrate. The stacked body includes conductive films and insulating films stacked alternately in a first direction. The conductive films and the insulating films are provided on the substrate and on the first insulating film. The first pillar pierces the stacked body in the first direction. The first pillar includes a first lower end portion and a first extension portion. The first lower end portion is disposed inside the first insulating film. The first extension portion is disposed inside the stacked body.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: January 22, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Maegawa, Hiroshi Nakaki
  • Publication number: 20170271350
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a first insulating film, a stacked body, and a first pillar. At least a portion of an upper layer portion of the substrate is conductive. The first insulating film is provided in a portion of the substrate. The stacked body includes conductive films and insulating films stacked alternately in a first direction. The conductive films and the insulating films are provided on the substrate and on the first insulating film. The first pillar pierces the stacked body in the first direction. The first pillar includes a first lower end portion and a first extension portion. The first lower end portion is disposed inside the first insulating film. The first extension portion is disposed inside the stacked body.
    Type: Application
    Filed: June 5, 2017
    Publication date: September 21, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takashi MAEGAWA, Hiroshi NAKAKl
  • Patent number: 9698150
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a first insulating film, a stacked body, and a first pillar. At least a portion of an upper layer portion of the substrate is conductive. The first insulating film is provided in a portion of the substrate. The stacked body includes conductive films and insulating films stacked alternately in a first direction. The conductive films and the insulating films are provided on the substrate and on the first insulating film. The first pillar pierces the stacked body in the first direction. The first pillar includes a first lower end portion and a first extension portion. The first lower end portion is disposed inside the first insulating film. The first extension portion is disposed inside the stacked body.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: July 4, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Maegawa, Hiroshi Nakaki
  • Publication number: 20170117288
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a first insulating film, a stacked body, and a first pillar. At least a portion of an upper layer portion of the substrate is conductive. The first insulating film is provided in a portion of the substrate. The stacked body includes conductive films and insulating films stacked alternately in a first direction. The conductive films and the insulating films are provided on the substrate and on the first insulating film. The first pillar pierces the stacked body in the first direction. The first pillar includes a first lower end portion and a first extension portion. The first lower end portion is disposed inside the first insulating film. The first extension portion is disposed inside the stacked body.
    Type: Application
    Filed: March 3, 2016
    Publication date: April 27, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takashi MAEGAWA, Hiroshi NAKAKl
  • Patent number: 7142040
    Abstract: A stabilized power supply circuit includes a charge pump power supply circuit including four switching elements and a capacitor, and an error amplifier comparing the output voltage of the charge pump power supply circuit and a reference voltage and outputting an error signal on the basis of the difference therebetween. A current source is connected in series to the gate of a switching element formed of a MOSFET. The period during which electric charge is discharged from the gate is controlled in accordance with the error signal in order to maintain the output voltage constant.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: November 28, 2006
    Assignees: Device Engineering Co., Ltd., Torex Device Co., Ltd.
    Inventors: Takeshi Naka, Takashi Maegawa
  • Publication number: 20060146583
    Abstract: A stabilized power supply circuit includes a charge pump power supply circuit including four switching elements and a capacitor, and an error amplifier comparing the output voltage of the charge pump power supply circuit and a reference voltage and outputting an error signal on the basis of the difference therebetween. A current source is connected in series to the gate of a switching element formed of a MOSFET. The period during which electric charge is discharged from the gate is controlled in accordance with the error signal in order to maintain the output voltage constant.
    Type: Application
    Filed: March 26, 2004
    Publication date: July 6, 2006
    Inventors: Takeshi Naka, Takashi Maegawa