Patents by Inventor Takashi Magoi

Takashi Magoi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080197437
    Abstract: Provided is a solid-state imaging apparatus having excellent reading accuracy. The solid-state imaging apparatus of the present invention includes a solid-state imaging element (light receiving element portion) (1a) of a solid-state imaging element chip (1) mounted on a film (11), and a resin (2b) having fluidity between the solid-state imaging element chip (1) and the film (11), in which the periphery of the resin having the fluidity is sealed with solid-state resins (2a, 14, etc.) that are said to be sealing members. The resin (2b) having the fluidity eliminates an adverse influence on reading due to waviness on the film surface, and realizes the solid-state imaging apparatus having the excellent reading accuracy.
    Type: Application
    Filed: February 13, 2008
    Publication date: August 21, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Tomonobu Sugimoto, Takashi Magoi
  • Patent number: 7262507
    Abstract: Semiconductor-mounted device comprises wired board, first semiconductor chip mounted on first side of wired board, second semiconductor chip mounted on second side of wired board and sealing resin sealing, with a same height, a region disposed at and around first semiconductor chip and opposite, across wired board, to at least an area of projecting electrodes of second semiconductor chip; and a producing method thereof. Semiconductor-mounted device also comprises wired board, first semiconductor chip mounted on first side of wired board, second semiconductor chip mounted on second side of wired board and resin sheet covering, at substantially a same height as first semiconductor chip, a region disposed around first semiconductor chip and opposite, across wired board, to at least an area of projecting electrodes of second semiconductor chip, back surface of first semiconductor chip being exposed; and a producing method thereof.
    Type: Grant
    Filed: December 27, 2004
    Date of Patent: August 28, 2007
    Assignee: NEC Electronics Corporation
    Inventors: Shigekazu Hino, Takashi Magoi, Syunichi Iwanaga
  • Publication number: 20050146026
    Abstract: Semiconductor-mounted device comprises wired board, first semiconductor chip mounted on first side of wired board, second semiconductor chip mounted on second side of wired board and sealing resin sealing, with a same height, a region disposed at and around first semiconductor chip and opposite, across wired board, to at least an area of projecting electrodes of second semiconductor chip; and a producing method thereof. Semiconductor-mounted device also comprises wired board, first semiconductor chip mounted on first side of wired board, second semiconductor chip mounted on second side of wired board and resin sheet covering, at substantially a same height as first semiconductor chip, a region disposed around first semiconductor chip and opposite, across wired board, to at least an area of projecting electrodes of second semiconductor chip, back surface of first semiconductor chip being exposed; and a producing method thereof.
    Type: Application
    Filed: December 27, 2004
    Publication date: July 7, 2005
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Shigekazu Hino, Takashi Magoi, Syunichi Iwanaga
  • Publication number: 20030150109
    Abstract: A circuit board is manufactured such that a laminated conductive pattern is formed directly on a surface of an insulating board made of a resin board by plating. The circuit board is subjected to heat treatment at temperatures higher than the softening point at which the resin board is softened and lower than a thermal point at which the conductive pattern is not displaced on the board. The circuit board manufactured in such a manner is able to have the insulating board and the conductive pattern strongly bonded to one another and to prevent displacement of laminated conductive pattern due to flow of resin.
    Type: Application
    Filed: February 6, 2003
    Publication date: August 14, 2003
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Takashi Magoi
  • Patent number: 6396203
    Abstract: A color shadow mask assembly includes a shadow mask spaced apart from an inner surface of a face panel by a predetermined gap and having a curved surface, and a rectangular frame for supporting and fixing the shadow mask. The shadow mask and the frame are integrally formed by welding to fix a side wall of the frame to a skirt of the face panel. The skirt alternately overlaps inner and outer surfaces of the side wall of the frame at opposite surfaces between the skirt of the shadow mask and the side wall of the frame.
    Type: Grant
    Filed: July 16, 1998
    Date of Patent: May 28, 2002
    Assignee: NEC Corporation
    Inventors: Nobumitsu Aibara, Akira Shishido, Takashi Magoi, Tadayuki Nishimura