Patents by Inventor Takashi Masuko

Takashi Masuko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240306308
    Abstract: A semiconductor package includes a wiring board and a semiconductor element mounted on the wiring board. The wiring board includes a first insulating material layer having a surface with an arithmetic average roughness Ra of 100 nm or less, a metal wiring provided on the surface of the first insulating material layer, and a second insulating material layer provided to cover the metal wiring. The metal wiring is configured by a metal layer in contact with the surface of the first insulating material layer and a conductive part stacked on a surface of the metal layer, and a nickel content rate of the metal layer is 0.25 to 20% by mass.
    Type: Application
    Filed: April 30, 2024
    Publication date: September 12, 2024
    Inventors: Masaya TOBA, Kazuhiko KURAFUCHI, Takashi MASUKO, Kazuyuki MITSUKURA, Shinichiro ABE
  • Patent number: 12004305
    Abstract: A wiring board according to the present disclosure includes a first insulating material layer having a surface with an arithmetic average roughness Ra of 100 nm or less, a metal wiring provided on the surface of the first insulating material layer, and a second insulating material layer provided to cover the metal wiring, in which the metal wiring is configured by a metal layer in contact with the surface of the first insulating material layer and a conductive part stacked on a surface of the metal layer, and a nickel content rate of the metal layer is 0.25 to 20% by mass.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: June 4, 2024
    Assignee: RESONAC CORPORATION
    Inventors: Masaya Toba, Kazuhiko Kurafuchi, Takashi Masuko, Kazuyuki Mitsukura, Shinichiro Abe
  • Patent number: 11979990
    Abstract: A method for manufacturing a wiring board according to the present disclosure includes: in the following order, (a) a step of irradiating an insulating layer composed of a resin composition with active energy rays; (b) a step of adsorbing an electroless plating catalyst to the insulating layer; and (c) a step of forming a metal layer on a surface of the insulating layer by electroless plating, in which in the step (a), a modified region having a thickness of 20 nm or more in a depth direction from the surface of the insulating layer and voids communicating from the surface of the insulating layer is formed by irradiation of the active energy rays.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: May 7, 2024
    Assignee: RESONAC CORPORATION
    Inventors: Masaya Toba, Kazuhiko Kurafuchi, Takashi Masuko, Kazuyuki Mitsukura, Shinichiro Abe
  • Publication number: 20240088051
    Abstract: A method for manufacturing a semiconductor device is disclosed. The method for manufacturing a semiconductor device includes preparing a base material, preparing a plurality of semiconductor elements each having a connection terminal, preparing a wiring board provided with a first wiring, arranging the plurality of semiconductor elements on the base material, covering the plurality of semiconductor elements on the base material with an insulating material, arranging the wiring board on at least one of the plurality of semiconductor elements so that the first wiring is connected to at least some of the connection terminals of the plurality of semiconductor elements covered with the insulating material, and forming a second wiring around the first wiring. The first wiring has finer wiring than the second wiring.
    Type: Application
    Filed: January 12, 2022
    Publication date: March 14, 2024
    Inventors: Kazuyuki MITSUKURA, Shunsuke OTAKE, Hiroaki FUJITA, Shinji SHIMAOKA, Takashi MASUKO, Kazuhiko KURAFUCHI
  • Publication number: 20230356498
    Abstract: An organic core material including a first layer having a first fiber cloth and a first resin layer formed from a first resin component and having the first fiber cloth embedded therein, and a second layer having a second fiber cloth and a second resin layer formed from a second resin component and having the second fiber cloth embedded therein. The organic core material has a laminated structure including the second layer, a plurality of the first layers, and the second layer in order, and a content percentage of the second resin component based on a mass of the second resin layer is higher than a content percentage of the first resin component based on a mass of the first resin layer.
    Type: Application
    Filed: September 15, 2021
    Publication date: November 9, 2023
    Inventors: Shunsuke OTAKE, Kazuyuki MITSUKURA, Takashi MASUKO, Kazuhiko KURAFUCHI, Shinji SHIMAOKA, Hiroaki FUJITA
  • Publication number: 20230253215
    Abstract: A method for producing a wiring board according to the present disclosure includes: (A) forming a first insulating material layer on a supporting substrate; (B) forming a first opening part in the first insulating material layer; (C) forming a seed layer on the first insulating material layer; (D) providing a resist pattern on a surface of the seed layer; (E) forming a wiring part including a pad and wiring; (F) removing the resist pattern; (G) removing the seed layer; (H) applying a first surface treatment to the surface of the pad; (I) forming a second insulating material layer; (J) forming a second opening part in the second insulating material layer; (K) applying a second surface treatment to the surface of the pad; and (L) heating the second insulating material layer to a temperature equal to or higher than the glass transition temperature of the second insulating material layer.
    Type: Application
    Filed: July 28, 2020
    Publication date: August 10, 2023
    Inventors: Masaya TOBA, Kazuhiko KURAFUCHI, Takashi MASUKO, Kazuyuki MITSUKURA
  • Patent number: 11636667
    Abstract: According to an embodiment, a pattern recognition apparatus includes an RNN layer, as a middle layer, that includes an input converting unit and an RNN processor. The input converting unit performs conversion, for each step, on an input vector and a recurrent input vector, and calculates and outputs a converted vector of which the number of dimensions is smaller than the sum of the numbers of dimensions of respective the input vector and the recurrent input vector. The input vector is formed of a feature vector output from an input layer or an output of the RNN processor included in a lower RNN layer. The recurrent input vector is formed of an output of a previous step of the RNN processor. The RNN processor calculates an RNN output vector from the converted vector calculated in the input converting unit and outputs the RNN output vector, for each step.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: April 25, 2023
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takashi Masuko
  • Patent number: 11330721
    Abstract: A resin film includes a resin composition for forming a flexible resin layer. The resin composition includes an elastomer, a polymerizable compound, and a polymerization initiator. A laminated film includes a base material film, a resin film formed on the base material film, and a protective film attached to the resin film.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: May 10, 2022
    Assignee: SHOWA DENKO MATERIALS CO., LTD
    Inventors: Tomoaki Shibata, Hanako Yori, Tomonori Minegishi, Hidenori Abe, Takashi Masuko, Shunsuke Otake
  • Publication number: 20220071018
    Abstract: A method for manufacturing a wiring board according to the present disclosure includes: in the following order, (a) a step of irradiating an insulating layer composed of a resin composition with active energy rays; (b) a step of adsorbing an electroless plating catalyst to the insulating layer; and (c) a step of forming a metal layer on a surface of the insulating layer by electroless plating, in which in the step (a), a modified region having a thickness of 20 nm or more in a depth direction from the surface of the insulating layer and voids communicating from the surface of the insulating layer is formed by irradiation of the active energy rays.
    Type: Application
    Filed: December 19, 2019
    Publication date: March 3, 2022
    Inventors: Masaya TOBA, Kazuhiko KURAFUCHI, Takashi MASUKO, Kazuyuki MITSUKURA, Shinichiro ABE
  • Publication number: 20220071019
    Abstract: A wiring board according to the present disclosure includes a first insulating material layer having a surface with an arithmetic average roughness Ra of 100 nm or less, a metal wiring provided on the surface of the first insulating material layer, and a second insulating material layer provided to cover the metal wiring, in which the metal wiring is configured by a metal layer in contact with the surface of the first insulating material layer and a conductive part stacked on a surface of the metal layer, and a nickel content rate of the metal layer is 0.25 to 20% by mass.
    Type: Application
    Filed: December 19, 2019
    Publication date: March 3, 2022
    Inventors: Masaya TOBA, Kazuhiko KURAFUCHI, Takashi MASUKO, Kazuyuki MITSUKURA, Shinichiro ABE
  • Patent number: 11147166
    Abstract: Disclosed is a method for producing a semiconductor device including a circuit board having a flexible resin layer that encapsulates a circuit component. The method may include a step of immersing a flexible substrate in an encapsulant, drying the encapsulant, and thereby encapsulating the circuit component with the encapsulant; and a step of curing the encapsulant, and thereby forming a flexible resin layer.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: October 12, 2021
    Assignee: SHOWA DENKO MATERIALS CO., LTD.
    Inventors: Tomoaki Shibata, Hanako Yori, Tomonori Minegishi, Hidenori Abe, Takashi Masuko, Shunsuke Otake
  • Patent number: 10964313
    Abstract: A word score calculation device according to an embodiment includes an input unit and a calculating unit. The input unit receives input of a string of words including known words, which are known already, and new words, which are not yet known. The calculating unit inputs the lexicon feature of a word, which is included in the string of words, in a neural network in which one or more unit groups for inputting the lexicon features of words are included in an input layer, and calculates a word score of the target word included in the string of words.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: March 30, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Terufumi Morishita, Takashi Masuko
  • Patent number: 10741184
    Abstract: According to an embodiment, an arithmetic operation apparatus for a neural network includes an input layer calculator, a correction unit calculator, a hidden layer calculator, and an output layer calculator. The input layer calculator is configured to convert an input pattern into features as outputs of an input layer. The correction unit calculator is configured to perform calculation on N unit groups corresponding respectively to N classes of the input pattern and including correction units that each multiply a value based on inputs by a weight determined for the corresponding class. The hidden layer calculator is configured to perform calculation in a hidden layer based on the outputs of the input layer, another hidden layer, or the correction unit calculator. The output layer calculator is configured to perform calculation in an output layer based on the calculation for the hidden layer or the outputs of the correction unit calculator.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: August 11, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Fujimura, Takashi Masuko
  • Publication number: 20200253059
    Abstract: Disclosed is a method for producing a semiconductor device including a circuit board having a flexible resin layer that encapsulates a circuit component. The method may include a step of immersing a flexible substrate in an encapsulant, drying the encapsulant, and thereby encapsulating the circuit component with the encapsulant; and a step of curing the encapsulant, and thereby forming a flexible resin layer.
    Type: Application
    Filed: April 21, 2020
    Publication date: August 6, 2020
    Inventors: Tomoaki SHIBATA, Hanako YORI, Tomonori MINEGISHI, Hidenori ABE, Takashi MASUKO, Shunsuke OTAKE
  • Patent number: 10674612
    Abstract: Disclosed is a method for producing a semiconductor device including a circuit board having a flexible resin layer that encapsulates a circuit component. The method may include a step of immersing a flexible substrate in an encapsulant, drying the encapsulant, and thereby encapsulating the circuit component with the encapsulant; and a step of curing the encapsulant, and thereby forming a flexible resin layer.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: June 2, 2020
    Assignee: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Tomoaki Shibata, Hanako Yori, Tomonori Minegishi, Hidenori Abe, Takashi Masuko, Shunsuke Otake
  • Patent number: 10553205
    Abstract: A speech recognition device includes one or more processors configured to calculate a score vector sequence on the basis of a speech signal, search a search model to detect a path following the input symbol from which a likely acoustic score in the score vector sequence is obtained, and output an output symbol allocated to the detected path. The symbol set includes a symbol representing a phonetic unit to be recognized, and an additional symbol representing at least one of a filler, a disfluency, and a non-speech sound. A search model includes an input symbol string arranged one or more input symbols, and paths to which output symbols are allocated. When the additional symbol is received as the input symbol from which the likely acoustic score is obtained, the processors start searching for a path associated with a new output symbol from a next score vector.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: February 4, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takashi Masuko
  • Patent number: 10540987
    Abstract: A summary generating device includes a featural script extracting unit, a segment candidate generating unit, and a structuring estimating unit. The featural script extracting unit extracts featural script information of the words included in text information. Based on the extracted feature script information, the segment candidate generating unit generates candidates of segments that represent the constitutional units for the display purpose. Based on the generated candidates of segments and based on an estimation model for structuring, the structuring estimating unit estimates structure information containing information ranging from information of a comprehensive structure level to information of a local structure level.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: January 21, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kosei Fume, Taira Ashikawa, Masayuki Ashikawa, Takashi Masuko
  • Patent number: 10452355
    Abstract: According to an embodiment, an automaton deforming device includes a transforming unit and a deforming unit. The transforming unit generates second values by transforming first values, which either represent weights assigned to transitions in a weighted finite state automaton or represent values that are transformed into weights assigned to transitions in a weighted finite state automaton, in such a way that number of elements of a set of the first values are reduced and an order of the first values is preserved. The deforming unit deforms a weighted finite state automaton in which weights according to the second values are assigned to transitions.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: October 22, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Manabu Nagao, Takashi Masuko
  • Patent number: 10410624
    Abstract: According to an embodiment, a training apparatus includes a converting unit to convert each input word into a vocabulary feature thereof based on a first probability associated with the input word, to acquire an input training word indicating the input word or the vocabulary feature, and convert, when an input training word string including input training words is input to an input layer of a neural network, an output word expected to be output from an output layer of the neural network into a vocabulary feature of the output word based on a second probability associated with the output word, to acquire an output training word indicating the output word or a vocabulary feature thereof; and a training unit to train the neural network based on a difference between an expected score of the output training word and a score output from a unit corresponding to the output training word.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: September 10, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Terufumi Morishita, Takashi Masuko
  • Patent number: 10269355
    Abstract: According to an embodiment, a data processing device generates result data which represents a result of performing predetermined processing on series data. The device includes an upper-level processor and a lower-level processor. The upper-level processor attaches order information to data blocks constituting the series data. The lower-level processor performs lower-level processing on the data blocks having the order information attached thereto, and attaches common order information, which is in common with the data blocks, to values obtained as a result of the lower-level processing. The upper-level processor integrates the values, which have the common order information attached thereto, based on the common order information and performs upper-level processing to generate the result data.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: April 23, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shoko Miyamori, Takashi Masuko, Mitsuyoshi Tachimori, Kouji Ueno, Manabu Nagao