Abstract: A surgical tool for positioning a surgical device includes a gripping portion; a rod protruding from the gripping portion; and a coupling system. The coupling system comprises an axial retention assembly comprising, at a free end of the rod, two opposite semispherical portions, wherein respective flat surfaces are separated from each other by an axial notch made partially along the rod, and a central clutch movable between a locking position and a disengagement position. In the locking position, the central clutch approaches the free end of the rod and is interposed between the two semispherical portions, preventing reciprocal approach thereof so as to block the two semispherical portions within a seat of said surgical device. In the disengagement position, the central clutch moves away from the free end such that the two semispherical portions can approach to allow the tool to come out of the surgical device.

Abstract: The present invention addresses the problem of providing a quantum bit cell and a quantum bit integrated circuit having an easy-to-integrate structure. The quantum bit cell of the present invention including a spin torque oscillator capable of emitting a microwave with a propagation distance of 1 ?m or less and having a maximum diameter of 1 ?m or less, and a solid-state element quantum bit arranged near the spin torque oscillator at an interval of the propagation distance or less, where a quantum two-level system is controlled by the microwave.

Abstract: An electronic apparatus wiring harness is provided that includes: a fixed-side casing and a moving-side casing, the moving-side casing being provided with a moving-side casing base which is rotatably journalled to the fixed-side casing, and a sliding portion which is provided so as to be slidable on a slide surface provided in the moving-side casing base. The circuit of the sliding portion and the circuit of the fixed-side casing are electrically connected together by an electric wire, which is a wiring harness having a flat cable portion having electric wire bodies arranged in parallel and formed in a tape shape having a jacket strip portion in which a number of the electric wire bodies are bundled; the flat cable portion is arranged in a bent manner so as to form a U shape on the slide surface of the moving-side casing base.

Abstract: A manufacturing method of the nano-wire field effect transistor, comprising steps of preparing an SOI substrate having a (100) surface orientation; processing a silicon crystal layer comprising the SOI substrate into a standing plate-shaped member having a rectangular cross-section; processing the silicon crystal layer by orientation dependent wet etching and thermal oxidation into a shape where two triangular columnar members are arranged one above the other with a spacing from each other so as to face along the ridge lines of the triangular columnar members; and processing the two triangular columnar members into a circular columnar member configuring a nano-wire by hydrogen annealing or thermal oxidation.

Abstract: Provided is a method for fabricating a nano-wire field effect transistor including steps of: preparing an SOI substrate having a (100) surface orientation, and nano-wire field effect transistor where two triangular columnar members configuring the nano-wires and being made of a silicon crystal layer are arranged one above the other on an SOI substrate having a (100) surface such a way that the ridge lines of the triangular columnar members face via an insulator; processing the silicon crystal configuring the SOI substrate into a standing plate-shaped member having a rectangular cross-section; and as a nanowire, processing the silicon crystal by orientation dependent wet etching into a shape where two triangular columnar members are arranged one above the other in such a way that the ridge lines of the triangular columnar members configuring the nano-wires face through the ridge lines thereof, and an integrated circuit including the nano-wire field effect transistor.

Abstract: A manufacturing method of the nano-wire field effect transistor, comprising steps of preparing an SOI substrate having a (100) surface orientation; processing a silicon crystal layer comprising the SOI substrate into a standing plate-shaped member having a rectangular cross-section; processing the silicon crystal layer by orientation dependent wet etching and thermal oxidation into a shape where two triangular columnar members are arranged one above the other with a spacing from each other so as to face along the ridge lines of the triangular columnar members; and processing the two triangular columnar members into a circular columnar member configuring a nano-wire by hydrogen annealing or thermal oxidation.

Abstract: A harness-integrated slide hinge is provided that connects between a plurality of casings having circuits therein while allowing the casings to move relatively. The harness-integrated slide hinge includes: a first sliding plate fitted to the one casing; a second sliding plate fitted to the other casing; a sliding mechanism that connects between the first sliding plate and the second sliding plate while allowing them to move relatively; and a harness that has a plurality of wirings, and connection sections provided on both ends of these wirings, and that is routed between the first sliding plate and the second sliding plate, wherein a wiring lamination section having a plurality of the wirings laminated therein is bent in a U-shape and accommodated in a space section between the first sliding plate and the second sliding plate.

Abstract: An SRAM device including a memory cell, the memory cell having two access transistors connected to a word line, and a flip-flop circuit having complementary transistors, the transistor being a field effect transistor having a standing semiconductor thin plate, a logic signal input gate and a bias voltage input gate, the gates sandwiching the semiconductor thin plate and being electrically separated from each other, a first bias voltage is applied to bias voltage input gates of the transistors of the memory cells in a row including a memory cell being accessed for reading or writing, and a second bias voltage is applied to the bias voltage input gates of the transistors of the memory cells in a row including a memory cell under memory holding operation.

Abstract: An electronic device includes at least first and second enclosures mounted so as to enable relative displacement therebetween, and an electric wire which electrically connects a circuit of the first enclosure and a circuit of the second enclosure. The electric wire includes a tape-shaped flat cable, including a plurality of internal wires arranged in parallel in a row.

Abstract: A connector is provided which includes a plug having a plurality of cables disposed on one side of the plug, and a socket mounted on a base substrate that is used to connect the plug. The plug includes a plate-like member and a flexible substrate fixed to the surroundings of the plate-like member. The plate-like member includes a planar portion approximately parallel to a substrate face of the base substrate, and a bent portion provided on the other side of the plug and extending in a direction approximately perpendicular to the base substrate. The socket includes a mating space which receives the bent portion from a direction approximately perpendicular to the base substrate when the plug and socket are connector-connected.

Abstract: A static random access memory (SRAM) cell includes a first to a fourth semiconductor thin plate that are provided on a substrate and are arranged parallel to each other. On respective semiconductor thin plates, there is formed a first four-terminal double-gate field effect transistor (FET) with a first conductivity type, a second and a third four-terminal double-gate FET which are connected in series with each other and have a second conductivity type, a fourth and a fifth four-terminal double-gate FET which are connected in series with each other and have the second conductivity type, and a sixth four-terminal double-gate FET with the first conductivity type. The third and the fourth four-terminal double-gate FETs form select transistors, and the first, second, fifth and sixth four-terminal double-gate FETs form a complementary metal-oxide-semiconductor (CMOS) inverter.

Abstract: A method of manufacturing a film antenna includes: a process of sticking a bonding surface of a bonding sheet to a surface of a metal thin film of a plastic film fitted with metal thin film; a process of forming the antenna circuit part by completely cutting the plastic film fitted with metal thin film in a thickness direction thereof from the bonding surface, and half-cutting the bonding sheet in a thickness direction thereof; a process of peeling away portions of the plastic film fitted with metal thin film around the antenna circuit part; a process of laminating a first flexible plastic film onto the plastic film fitted with metal thin film side; a process of peeling away the bonding sheet; and a process of laminating a second flexible plastic film onto the surface of the metal thin film.

Abstract: A field-effect transistor comprising a movable gate electrode that suppresses a leakage current from the gate electrode, and has a large current drivability and a low leakage current between a source and a drain. The field-effect transistor comprises: an insulating substrate; a semiconductor layer of triangle cross-sectional shape formed on the insulating substrate, having a gate insulation film on a surface, and forming a channel in a lateral direction; fixed electrodes that are arranged adjacent to both sides of the semiconductor layer and in parallel to the semiconductor layer, each of the electrodes having an insulation film on a surface; a source/drain formed at the end part of the semiconductor layer; and the movable gate electrode formed above the semiconductor layer and the fixed electrodes with a gap.

Abstract: An electronic apparatus includes: a plurality of casings that are mounted so as to be movable relative to each other and have circuits provided therein; and an electric wire that electrically connects the circuits provided in the casings. The electronic wire has a harness structure that includes a plurality of wires and connection portions provided at both ends of each of the plurality of wires, and connection portions of the casings to the harness are arranged such that a line linking the connection portions is not parallel to a direction in which the plurality of casings are moved.

Abstract: Provided is a method for fabricating a nano-wire field effect transistor including steps of: preparing an SOI substrate having a (100) surface orientation, and nano-wire field effect transistor where two triangular columnar members configuring the nano-wires and being made of a silicon crystal layer are arranged one above the other on an SOI substrate having a (100) surface such a way that the ridge lines of the triangular columnar members face via an insulator; processing the silicon crystal configuring the SOI substrate into a standing plate-shaped member having a rectangular cross-section; and as a nanowire, processing the silicon crystal by orientation dependent wet etching into a shape where two triangular columnar members are arranged one above the other in such a way that the ridge lines of the triangular columnar members configuring the nano-wires face through the ridge lines thereof, and an integrated circuit including the nano-wire field effect transistor.

Abstract: Provided is a method for fabricating a nano-wire field effect transistor including steps of: preparing a nano-wire field effect transistor including two columnar members made of a silicon crystal configuring a nano-wire on a substrate are arranged on a substrate in parallel and one above the other, and an SOI substrate having a (100) surface orientation; processing a silicon crystal layer configuring the SOI substrate into a standing plate-shaped member having a rectangular cross-section; processing the silicon crystal by orientation dependent wet etching and thermal oxidation into a shape where two triangular columnar members are arranged one above the other with a spacing from each other as to face along the ridge lines of the triangular columnar members; and processing the triangular columnar member into a circular columnar member configuring a nano-wire by hydrogen-annealing or a thermal oxidation; and an integrated circuit including the transistor.

Abstract: An SRAM device comprising a memory cell, the memory cell comprising two access transistors connected to a word line, and a flip-flop circuit having complementary transistors, the transistor being a field effect transistor having a standing semiconductor thin plate, a logic signal input gate and a bias voltage input gate, the gates sandwiching the semiconductor thin plate and being electrically separated from each other, and wherein a first bias voltage is applied to bias voltage input gates of the transistors of the memory cells in a row including a memory cell being accessed for reading or writing such that the threshold voltage on the logic signal input gates of the transistors is set at low level, and a second bias voltage is applied to the bias voltage input gates of the transistors of the memory cells in a row including a memory cell under memory holding operation such that the threshold voltage on the logic signal input gates of the transistors is set at high level.

Abstract: In an SRAM cell including a first to a fourth semiconductor thin plates which stand on a substrate and are arranged in parallel to each other, on each of the four semiconductor thin plates being formed a first four-terminal double-gate FET with a first conductivity type; a second and a third four-terminal double-gate FETs which are connected in series with each other and have a second conductivity type; a fourth and a fifth four-terminal double-gate FETs which are connected in series with each other and have the second conductivity type; a sixth four-terminal double-gate FET with the first conductivity type, wherein the third and the fourth four-terminal double-gate FETs form select transistors, and the first, the second, the fifth and the sixth four-terminal double-gate FETs form a CMOS inverter, logic signal input gates of the first and the sixth four-terminal double-gate FETs are arranged on the side facing the second and the third semiconductor thin plates, respectively, while threshold voltage control ga

Abstract: A harness-integrated slide hinge is provided that connects between a plurality of casings having circuits therein while allowing the casings to move relatively. The harness-integrated slide hinge includes: a first sliding plate fitted to the one casing; a second sliding plate fitted to the other casing; a sliding mechanism that connects between the first sliding plate and the second sliding plate while allowing them to move relatively; and a harness that has a plurality of wirings, and connection sections provided on both ends of these wirings, and that is routed between the first sliding plate and the second sliding plate, wherein a wiring lamination section having a plurality of the wirings laminated therein is bent in a U-shape and accommodated in a space section between the first sliding plate and the second sliding plate.

Abstract: An electronic apparatus wiring harness is provided that includes: a fixed-side casing and a moving-side casing each having a circuit and rotatably journalled by a shaft having a through hole at its center, the moving-side casing being provided with a moving-side casing base which is rotatably journalled to the fixed-side casing, and a sliding portion which is provided so as to be slidable on a slide surface provided in the moving-side casing base. The circuit of the sliding portion and the circuit of the fixed-side casing are electrically connected together by an electric wire. The electric wire is a wiring harness having a flat cable portion in which a number of electric wire bodies are arranged in parallel and which is formed in a tape shape by jackets, and a jacket strip portion in which a number of the electric wire bodies are bundled; the flat cable portion is arranged in a bent manner so as to form a U shape on the slide surface of the moving-side casing base.