Patents by Inventor Takashi Miyagawa

Takashi Miyagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11751480
    Abstract: An electronic device includes a support substrate, a piezoelectric layer that is provided on the support substrate, a functional element including an electrode provided on a surface of the piezoelectric layer, a metallic frame body that is provided on the support substrate so as to surround the piezoelectric layer and the functional element in a plan view, a metallic lid that is provided on the frame body so as to form a space between the lid and the support substrate, and seals the functional element into the space, and a columnar body that is provided between the support substrate and the lid in the space.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: September 5, 2023
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Ryouta Iwabuchi, Motoi Yamauchi, Takashi Miyagawa, Tsutomu Kikuchi, Yuki Maruya
  • Patent number: 11706991
    Abstract: An electronic device includes a support substrate, a piezoelectric layer that is provided on the support substrate, a functional element including an electrode provided on a surface of the piezoelectric layer, a metallic frame body that is provided on the support substrate so as to surround the piezoelectric layer and the functional element in a plan view, a metallic lid that is provided on the frame body so as to form a space between the lid and the support substrate, and seals the functional element into the space, and a columnar body that is provided between the support substrate and the lid in the space.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: July 18, 2023
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Ryouta Iwabuchi, Motoi Yamauchi, Takashi Miyagawa, Tsutomu Kikuchi, Yuki Maruya
  • Publication number: 20210098683
    Abstract: An electronic device includes a support substrate, a piezoelectric layer that is provided on the support substrate, a functional element including an electrode provided on a surface of the piezoelectric layer, a metallic frame body that is provided on the support substrate so as to surround the piezoelectric layer and the functional element in a plan view, a metallic lid that is provided on the frame body so as to form a space between the lid and the support substrate, and seals the functional element into the space, and a columnar body that is provided between the support substrate and the lid in the space.
    Type: Application
    Filed: September 11, 2020
    Publication date: April 1, 2021
    Applicant: TAIYO YUDEN CO., LTD.
    Inventors: Ryouta IWABUCHI, Motoi YAMAUCHI, Takashi MIYAGAWA, Tsutomu KIKUCHI, Yuki MARUYA
  • Patent number: 10199562
    Abstract: A method of fabricating an electronic device, the method including: arranging a device chip with no bump located on a lower surface of the device chip on a mounting substrate including a bump located on an upper surface of the mounting substrate; and bonding a pad located on the lower surface of the device chip and the bump by applying an ultrasonic wave to the device chip from an upper surface of the device chip.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: February 5, 2019
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Shinji Yamamoto, Jumpei Konno, Takashi Miyagawa
  • Publication number: 20180033952
    Abstract: A method of fabricating an electronic device, the method including: arranging a device chip with no bump located on a lower surface of the device chip on a mounting substrate including a bump located on an upper surface of the mounting substrate; and bonding a pad located on the lower surface of the device chip and the bump by applying an ultrasonic wave to the device chip from an upper surface of the device chip.
    Type: Application
    Filed: July 11, 2017
    Publication date: February 1, 2018
    Applicant: TAIYO YUDEN CO., LTD.
    Inventors: Shinji YAMAMOTO, Jumpei KONNO, Takashi MIYAGAWA
  • Patent number: 9858181
    Abstract: A memory module having different types of memory mounted together on a double-sided substrate has a first edge and opposite second edge and includes a plurality of memory controllers, a plurality of flash memories, and a plurality of second memories having a higher signal transmission rate than the flash memories. A socket terminal for connecting the double-sided substrate to a motherboard is formed on the front surface and the back surface of the double-sided substrate on the first edge side; the memory controllers are disposed on the second edge side; the second memories are disposed on the second edge side at positions opposite the positions at which the memory controllers are disposed; and the flash memories are disposed on at least the back surface thereof at positions that are closer to the first edge than are the positions at which the memory controllers and the second memories are disposed.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: January 2, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Yutaka Uematsu, Satoshi Muraoka, Hiroshi Kakita, Akio Idei, Yusuke Fukumura, Satoru Watanabe, Takayuki Ono, Taishi Sumikura, Yuichi Fukuda, Takashi Miyagawa, Michinori Naito, Hideki Osaka, Masabumi Shibata, Hitoshi Ueno, Kazunori Nakajima, Yoshihiro Kondo
  • Patent number: 9658783
    Abstract: In methods connecting a memory module configured from DRAM, which is high-speed memory, and a memory module configured from flash memory which is slower than DRAM but is high-capacity memory, to a CPU memory bus, in the case of sequential reading, the busy rate of the CPU memory bus increases, and performance degradation occurs easily. In the present invention, an information processing device has a CPU, a CPU memory bus, and a primary storage device. The primary storage device has a first memory module and a second memory module. The first memory module has high-speed memory. The second memory module has memory having the same memory interface as that of the high-speed memory, high-capacity memory having a different memory interface from that of the high-speed memory, and a controller that controls same. The first memory module and second memory module are caused to be accessed by the memory interface of the high-speed memory.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: May 23, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Satoshi Muraoka, Yutaka Uematsu, Hideki Osaka, Yuusuke Fukumura, Satoru Watanabe, Masabumi Shibata, Hiroshi Kakita, Yuichi Fukuda, Takashi Miyagawa, Michinori Naito, Hitoshi Ueno, Akio Idei, Takayuki Ono, Taishi Sumikura
  • Patent number: 9569144
    Abstract: When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: February 14, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Yutaka Uematsu, Satoshi Muraoka, Hideki Osaka, Masabumi Shibata, Yuusuke Fukumura, Satoru Watanabe, Hiroshi Kakita, Akio Idei, Hitoshi Ueno, Takayuki Ono, Takashi Miyagawa, Michinori Naito, Taishi Sumikura, Yuichi Fukuda
  • Publication number: 20160092351
    Abstract: A memory module having different types of memory mounted together on a double-sided substrate has a first edge and opposite second edge and includes a plurality of memory controllers, a plurality of flash memories, and a plurality of second memories having a higher signal transmission rate than the flash memories. A socket terminal for connecting the double-sided substrate to a motherboard is formed on the front surface and the back surface of the double-sided substrate on the first edge side; the memory controllers are disposed on the second edge side; the second memories are disposed on the second edge side at positions opposite the positions at which the memory controllers are disposed; and the flash memories are disposed on at least the back surface thereof at positions that are closer to the first edge than are the positions at which the memory controllers and the second memories are disposed.
    Type: Application
    Filed: June 20, 2013
    Publication date: March 31, 2016
    Inventors: Yutaka UEMATSU, Satoshi MURAOKA, Hiroshi KAKITA, Akio IDEI, Yusuke FUKUMURA, Satoru WATANABE, Takayuki ONO, Taishi SUMIKURA, Yuichi FUKUDA, Takashi MIYAGAWA, Michinori NAITO, Hideki OSAKA, Masabumi SHIBATA, Hitoshi UENO, Kazunori NAKAJIMA, Yoshihiro KONDO
  • Publication number: 20150355846
    Abstract: When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal.
    Type: Application
    Filed: March 27, 2013
    Publication date: December 10, 2015
    Inventors: Yutaka UEMATSU, Satoshi MURAOKA, Hideki OSAKA, Masabumi SHIBATA, Yuusuke FUKUMURA, Satoru WATANABE, Hiroshi KAKITA, Akio IDEI, Hitoshi UENO, Takayuki ONO, Takashi MIYAGAWA, Michinori NAITO, Taishi SUMIKURA, Yuichi FUKUDA
  • Publication number: 20150347032
    Abstract: In methods connecting a memory module configured from DRAM, which is high-speed memory, and a memory module configured from flash memory which is slower than DRAM but is high-capacity memory, to a CPU memory bus, in the case of sequential reading, the busy rate of the CPU memory bus increases, and performance degradation occurs easily. In the present invention, an information processing device has a CPU, a CPU memory bus, and a primary storage device. The primary storage device has a first memory module and a second memory module. The first memory module has high-speed memory. The second memory module has memory having the same memory interface as that of the high-speed memory, high-capacity memory having a different memory interface from that of the high-speed memory, and a controller that controls same. The first memory module and second memory module are caused to be accessed by the memory interface of the high-speed memory.
    Type: Application
    Filed: March 27, 2013
    Publication date: December 3, 2015
    Inventors: Satoshi MURAOKA, Yutaka UEMATSU, Hideki OSAKA, Yuusuke FUKUMURA, Satoru WATANABE, Masabumi SHIBATA, Hiroshi KAKITA, Yuichi FUKUDA, Takashi MIYAGAWA, Michinori NAITO, Hitoshi UENO, Akio IDEI, Takayuki ONO, Taishi SUMIKURA
  • Patent number: 8969173
    Abstract: A method of fabricating an electronic component includes: mounting a device chip on an upper surface of an insulative substrate; forming a sealing portion that seals the device chip; cutting the insulative substrate and the sealing portion; and forming a plated layer covering the sealing portion by barrel plating.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: March 3, 2015
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Yasuyuki Oda, Kaoru Sakinada, Takashi Miyagawa
  • Patent number: 8749114
    Abstract: An acoustic wave device includes, a substrate, an acoustic wave device chip that has a vibration part exciting an acoustic wave and is mounted on a surface of the substrate so that the vibration part is exposed to a space formed between the substrate and the acoustic wave device chip, and a joining part that is provided so as to surround the vibration part and joins the substrate and the acoustic wave device chip together. The joining part includes a first member made of solder, and a second member that is stacked on the first member and is made of a substance having a melting point higher than the solder. The second member has a thickness larger than a coplanarity of the surface of the substrate.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: June 10, 2014
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Kazushige Hatakeyama, Takashi Miyagawa
  • Publication number: 20140087090
    Abstract: A method for manufacturing a pattern structure includes the steps of forming a lift-off material on a base by an inkjet technique, forming a functional film on the base and the lift-off material by atomic layer deposition, and removing the lift-off material by a lift-off technique so as to form a pattern on the base from the functional film.
    Type: Application
    Filed: May 16, 2012
    Publication date: March 27, 2014
    Inventors: Takashi Miyagawa, Tetsuya Murakami, Kimiyasu Okamoto
  • Publication number: 20130337610
    Abstract: A method of fabricating an electronic component includes: mounting a device chip on an upper surface of an insulative substrate; forming a sealing portion that seals the device chip; cutting the insulative substrate and the sealing portion; and forming a plated layer covering the sealing portion by barrel plating.
    Type: Application
    Filed: June 14, 2013
    Publication date: December 19, 2013
    Inventors: Yasuyuki ODA, Kaoru SAKINADA, Takashi MIYAGAWA
  • Publication number: 20120181898
    Abstract: An acoustic wave device includes, a substrate, an acoustic wave device chip that has a vibration part exciting an acoustic wave and is mounted on a surface of the substrate so that the vibration part is exposed to a space formed between the substrate and the acoustic wave device chip, and a joining part that is provided so as to surround the vibration part and joins the substrate and the acoustic wave device chip together. The joining part includes a first member made of solder, and a second member that is stacked on the first member and is made of a substance having a melting point higher than the solder. The second member has a thickness larger than a coplanarity of the surface of the substrate.
    Type: Application
    Filed: January 18, 2012
    Publication date: July 19, 2012
    Applicant: TAIYO YUDEN CO., LTD.
    Inventors: Kazushige HATAKEYAMA, Takashi MIYAGAWA
  • Patent number: 6141844
    Abstract: A resonator device having an insulating substrate, a strip-shaped vibrating element which is mounted on said insulating substrate and is provided with driving electrodes formed on the main opposing surfaces of a piezoelectric substrate, and terminal electrodes which are provided on said insulating substrate so as to be electrically connected with said driving electrodes and to which driving signals are applied by an external signal source. At least the longitudinal side portions of said vibrating element are coated with a surface active agent. With such a constitution, fluctuations in resonant resistance which are due to the excitation level can be suppressed, thereby contributing to the stable operation of the device, reducing the number of producing steps, and raising the yield rate in production.
    Type: Grant
    Filed: February 13, 1998
    Date of Patent: November 7, 2000
    Assignee: Fujitsu Limited
    Inventors: Takashi Miyagawa, Masanori Yachi
  • Patent number: 5889357
    Abstract: The substrate for devices 10 comprises an insulating substrate 12 of an insulating material, conducting layers 14 formed on the insulating substrate 12 and opposed to each other at a certain distance, and a dielectric film 16 formed on that portion of the insulating substrate 12 between the conducting layers 14. The substrate 10 incorporates a capacitance constituted by the opposed electric layers 14 and the dielectric film 16. A piezoelectric oscillator 20 is connected to the left and right conducting layers 14b, 14c of the substrate for devices 10. A cap 22 is connected to a boundary part of the substrate 10 through epoxy resin 24. The substrate for devices 10 with a built-in capacitance can reduce fabrication costs of a piezoelectric oscillation device and a surface acoustic wave device.
    Type: Grant
    Filed: December 6, 1995
    Date of Patent: March 30, 1999
    Assignee: Fujitsu Limited
    Inventors: Masanori Yachi, Takashi Miyagawa, Takayuki Fujii, Masaaki Ono
  • Patent number: 5828159
    Abstract: A resonator device having an insulating substrate, a strip-shaped vibrating element which is mounted on said insulating substrate and is provided with driving electrodes formed on the main opposing surfaces of a piezoelectric substrate, and terminal electrodes which are provided on said insulating substrate so as to be electrically connected with said driving electrodes and to which driving signals are applied by an external signal source. At least the longitudinal side portions of said vibrating element are coated with a surface active agent. With such a constitution, fluctuations in resonant resistance which are due to the excitation level can be suppressed, thereby contributing to the stable operation of the device, reducing the number of producing steps, and raising the yield rate in production.
    Type: Grant
    Filed: June 4, 1997
    Date of Patent: October 27, 1998
    Assignee: Fujitsu Limited
    Inventors: Takashi Miyagawa, Masanori Yachi
  • Patent number: 5676324
    Abstract: A traverse device for simultaneous winding of yam packages in a spinning machine, which device can suppress the flexural vibration generated in a long rod. The traverse device incorporates a number of yarn guides 5 attached to a long, reciprocally moving rod 13 that is connected to a cam box 12 and in which a number of packages P are formed simultaneously. In particular, this device has an arrangement of a damping material 15 inside the rod 13, which is formed from a hollow pipe, and rapidly attenuates the vibration generated in the rod by the mechanical shock occurring at both ends of a reciprocal movement thereof.
    Type: Grant
    Filed: February 23, 1996
    Date of Patent: October 14, 1997
    Assignee: Murata Kikai Kabushiki Kaisha
    Inventor: Takashi Miyagawa