Abstract: A processor system (200) includes one task execution unit (220), another task execution unit (250), and a flag storage unit (230) provided with a control unit (232) and a flag area (234). When flag information stored in the flag area (234) does not satisfy a predetermined condition, the one task execution unit (220) outputs, to the control unit (232), a signal indicating that the flag information is being monitored, and suspends access to the flag information. The control unit (232) monitors the presence or absence of access to the flag information from the other task execution unit (250), and when there is access to the flag information, the control unit (232) outputs, to the one task execution unit (220), an instruction to release the suspension of access to the flag information.

Abstract: A vector processing unit includes a vector unit having a plurality of operation pipelines and a vector register connected to the plurality of operation pipelines, a scalar unit having a buffer, and a memory unit. A memory unit controller, which is connected between the memory unit and the vector unit and between the memory unit and the scalar unit, performs an information transfer in accordance with a serializing process among access requests by using a post instruction and a wait instruction. The access requests sandwiched between the post instruction and the wait instruction are serially carried out whereby the memory unit is serially accessed. A first unit assigns a post mark to each of access requests of vector store instructions that are issued during a time when the post instruction is being executed, and stops instruction execution of the scalar unit when there is a vector store instruction proceeding to the post instruction.