Patents by Inventor Takashi Morimoto

Takashi Morimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5462997
    Abstract: An epoxy resin composition contains (a) an epoxy resin represented by the general formula (2) ##STR1## wherein R.sub.1 to R.sub.4 independently represent hydrogen, an alkyl or cycloalkyl group having 1 to 9 carbon atoms, or halogen, and X represents hydrogen, an alkyl group having 1 to 9 carbon atoms, or an aryl and n represents an average number of repeating units of 0.1 to 1.6; and a curing agent.
    Type: Grant
    Filed: October 27, 1994
    Date of Patent: October 31, 1995
    Assignee: Sumitomo Chemical Co., Ltd.
    Inventors: Noriaki Saito, Takashi Morimoto, Kazuo Takebe, Yutaka Shiomi, Shigeki Naitoh, Shuichi Kanagawa
  • Patent number: 5395912
    Abstract: There is provided an epoxy resin composition represented by the general formula: ##STR1## wherein R.sub.1 represents an alkyl or cycloalkyl group having 1 to 9 carbon atoms, or halogen, R.sub.2 to R.sub.4 independently represent hydrogen, an alkyl or cycloalkyl group having 1 to 9 carbon atoms, or halogen, and X represents hydrogen, an alkyl group having 1 to 9 carbon atoms, or an aryl group, and n represents an average number of repeating units of 0.1 to 1.6. Cured products prepared from the epoxy resin have a lower hygroscopicity and a balance between thermal resistance and curing performance.
    Type: Grant
    Filed: November 22, 1993
    Date of Patent: March 7, 1995
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Noriaki Saito, Takashi Morimoto, Kazuo Takebe, Yutaka Shiomi, Shigeki Naitoh, Shuichi Kanagawa
  • Patent number: 5382532
    Abstract: A method for fabricating semiconductor devices wherein polysilicon gates for complementary-type field-effect semiconductor devices are formed of polysilicon to which impurity doped simultaneously to the polysilicon deposition; the both gates having the dual N.sup.+ /P.sup.+ polysilicon gate structure, so that the both N- and P-channel transistors are formed as the surface-channel type ones; and therefore, the off-characteristic, the short channel effect, and the controllability of threshold voltage are progressed. More specifically, N- and P-channel MISFETs are provided on a common semiconductor substrate (1); N-type polysilicon (9) doped with N-type impurity is adopted as the gate electrode for the N-channel MISFET; P-type polysilicon (8) doped with P-type impurity is adopted as the gate electrode for the P-channel MISFET; and a narrow region preventing the mutual diffusion of impurities is provided between portions of respective polysilicon.
    Type: Grant
    Filed: September 16, 1992
    Date of Patent: January 17, 1995
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Toshio Kobayashi, Yukio Okazaki, Masayasu Miyake, Hiroshi Inokawa, Takashi Morimoto
  • Patent number: 5267917
    Abstract: A rotary element engaging device of an automatic transmission includes a stationary member, a planetary gear set having rotary elements, a frictionally engaging element interposed between the stationary member and one of the rotary elements, a one-way clutch interposed between the stationary member and the one rotary element, and an operating member for engaging and disengaging the frictionally engaging element. The rotary element is adapted to be selectively engaged with the stationary member through two paths formed of the frictionally engaging element and the one-way clutch. The one-way clutch is disposed between the frictionally engaging element and the operating member. The one-way clutch includes an inner race connected to the one rotary element and an outer race fixed to the stationary member. The operating member is adapted to act on the frictionally engaging element through the outer race.
    Type: Grant
    Filed: October 23, 1992
    Date of Patent: December 7, 1993
    Assignees: Aisen Aw Co., Ltd., Toyota Jidosha Kabushiki Kaisha
    Inventors: Masanori Kadotani, Masahiro Haybuchi, Takashi Morimoto, Kazumasa Tsukamoto, Yasuo Hojo, Hidehiro Oba, Yutaka Taga
  • Patent number: 5086145
    Abstract: Disclosed is a method of manufacturing solvent-soluble polyorganosilsesquioxanes of the formula; ##STR1## wherein each R is a substituted or unsubstituted alkyl, alkenyl or halogen-substituted alkyl group of 1-5 carbon atoms, or substituted or unsubstituted phenyl of 6-10 carbon atoms, and n is 2-10,000; which comprises reacting an organotriacetoxysilane with a stoichiometric quantity of alcohol and/or water in an organic solvent to obtain a diacetoxymonoalkoxysilane, which is condensation polymerized in the presence of sodium hydrogencarbonate to obtain a prepolymer, which prepolymer is then condensation polymerized by heat in the presence of a catalyst selected from alkali metal hydroxides, alkaline earth metal hydroxides, alkali metal fluorides, alkaline earth metal fluorides and triethylamine.
    Type: Grant
    Filed: June 18, 1990
    Date of Patent: February 4, 1992
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Takashi Morimoto, Hiroshi Yoshioka
  • Patent number: 5039771
    Abstract: An oligomeric cage-like poly(silsesquioxane) of the general formula ##STR1## in which R is a monovalent hydrocarbon group and m is 4 to 12, can be polymerized by being admixed with a catalyst, e.g. alkali hydroxide or fluoride, and irradiated with microwaves. Different from conventional method of thermal polymerization, the polymerization reaction proceeds very uniformly at a high velocity to give a polymer of a high average molecular weight and narrow molecular weight distribution.
    Type: Grant
    Filed: January 16, 1989
    Date of Patent: August 13, 1991
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Takashi Morimoto, Hiroshi Yoshioka
  • Patent number: 4448800
    Abstract: A semiconductor manufacturing method which uses a refractory metal as a lift-off material and employs, in combination, a dry etching process suitable for forming a miniature pattern without undercutting and a film deposition method for deposing the lift-off material with directionality in a direction perpendicular to the substrate surface. A semiconductor device is fabricated by a lift-off method which is free from the fear of contamination, permits easy lift off of the lift-off material, even if large in area, and hence suitable for the formation of a high-density pattern.
    Type: Grant
    Filed: July 30, 1982
    Date of Patent: May 15, 1984
    Assignee: Nippon Telegraph and Telephone Public Corporation
    Inventors: Kohei Ehara, Susumu Muramoto, Takashi Morimoto, Seitaro Matsuo, Manabu Itsumi