Abstract: A signal processing device having a feature of analog-to-digital converting a burst signal has a feature of selecting data bus to notify a disk control device 2 of a conversion result via an NRZ data bus. The disk control device 2 includes means for storing the result of the analog-to-digital conversion of said servo positional signal. The positional signal of a head of the disk device is digitalized in an R/W channel. Sampling for digital conversion is performed in only a window which is defined only in the vicinity of peaks of the positional signal. The values of peaks which are obtained by sampling are averaged by an averaging circuit. This enables the influence of noise occurred outside of the window to be eliminated. Although the noise in the window is sampled, its adverse influence is suppressed by the averaging processing.

Abstract: A tool for allowing a user to take exercise, includes: an exercise amount measuring unit for measuring an exercise amount of the user; a data storing unit for storing a predetermined character string or image; and an output unit for outputting the predetermined character string or image stored in the data storing unit when the exercise amount measured by the exercise measuring unit has reached a predetermined exercise amount.

Abstract: A signal processing device for analog-to-digital converting a burst signal has a feature of selecting a data bus to notify a disk control device of a conversion result via an NRZ data bus. The disk control device stores the result of the analog-to-digital conversion of the servo positional signal. The positional signal of a head of the disk device is digitalized in a R/W channel. Sampling for digital conversion is performed in only a window which is defined only in the vicinity of peaks of the positional signal. The values of peaks which are obtained by sampling are averaged by an averaging circuit. This enables the influence of noise occurred outside of the window to be eliminated. Although the noise in the window is sampled, its adverse influence is suppressed by the averaging processing.

Abstract: The computer system includes a host system, a recording medium, and a digital signal decoder connected to the host system and the recording medium. The digital signal decoder receives M-bit data and generates an N-bit code word from the M-bit data. The number of consecutive bits of 1 in the code word is not larger than a first predetermined number K, and the number of consecutive bits of 0 is not larger than a second predetermined number L. When data is recorded/reproduced by a method such as NRZI (Non-Return to Zero Inverted), or the like, there is a defect in that the number of transitions of data is larger in a code with a high data encoding rate, and the run length of zero is long thereby increasing the data decoding error rate with the recording/reproducing of data. In the digital signal decoder according to the present invention, any code word includes at most 3 consecutive bits of 1, and at most 11 consecutive bits of 0, so that the data decoding error rate can be reduced.

Abstract: A variable logic cell and a variable analog cell are provided in a zone on a semiconductor chip other than block formation zones of original function circuits. The variable logic cell includes a variable logic circuit for outputting a logic output, a variable wiring circuit for enabling connection of the variable logic circuit with another variable logic circuit or an analog generation circuit, and a wiring-line connection state memory circuit for storing states of switching elements of the variable wiring circuit. The variable analog cell includes an analog generation circuit having a resistive element and a capacitive element for generating a voltage, a variable wiring circuit for connecting the analog generation circuit with another analog generation circuit or variable logic circuit, and a wiring-line connection state memory circuit for storing states of the switching elements of the variable wiring circuit.

Abstract: A transconductance control circuit is composed of a replica transconductance amplifier and resistance, a reference voltage source, first selectors, a differential amplifier, a voltage-current translate circuit with characteristics equal to the transconductance amplifier which constitutes analog filters. A first switch of the first selectors is connectable for the reference voltage source, and every constant period is made to connect it using clocks at the reference voltage source. A second switch of second selectors is connectable for plural capacitors, and every constant period is made to connect it using clocks at the capacitors.

Abstract: In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.

Abstract: A signal processing device having a feature of analog-to-digital converting a burst signal has a feature of selecting a data bus to notify a disk control device of a conversion result via an NRZ data bus. The disk control device stores the result of the analog-to-digital conversion of the servo positional signal. The positional signal of a head of the disk device is digitalizes in a R/W channel. Sampling for digital conversion is performed in only a window which is defined only in the vicinity of peaks of the positional signal. The values of peaks which are obtained by sampling are averaged by an averaging circuit. This enables the influence of noise occurred outside of the window to be eliminated. Although the noise in the window is sampled, its adverse influence is suppressed by the averaging processing.

Abstract: A calculation concerning the input of a signal is removed from a branch metric calculation processing on a trellis diagram of an extended partial response class, and the calculation of branch metrics and the selection of survivor paths can be carried out by the subtraction of the survivor paths and the comparison of constants.

Abstract: Digital information including a sync data field and a user data field subsequent thereto is read from a storage media as a digital information signal in an analog signal format. The obtained signal is sampled according to a clock signal and is thereby transformed into a digital information signal in a digital format. In the sync data field, the clock signal is synchronized with the digital information signal by an analog PLL circuit. Thereafter, in the user data field, the clock signal is synchronized with the digital information signal by a digital PLL circuit.

Abstract: A signal processing delay circuit is fabricated as a semiconductor integration circuit to cope with increase in the data transfer speed and data recording and reproducing density on a recording medium. In the delay circuit, the amount of delay of a reference delay circuit of a delay PLL is controlled to take a fixed value independent of deviation in quality of the semiconductor circuit, change in power, and alteration in temperature. A control signal supervising the delay amount of the reference delay circuit is employed to control amounts of delay of input signals supplied to a window adjustment delay circuit of a window adjustment circuit and a T/2 generation delay circuit generating a synchronizing signal. Each of these delay circuits includes an analog variable delay circuit having the same configuration. The window adjustment delay circuit is supervised by a signal obtained by weighting the control signal by a D/A converter.

Abstract: A system for reproducing data recorded on a magnetic recording medium at high density is provided as a simple configuration. Quadripartite reproduction data is output from a Viterbi detection circuit to an adder, which then subtracts the quadripartite reproduction data from a signal before PR4-ML method data determination. An adder is used to perform a (1+D) process for the result. An error signal pattern detection circuit performs maximum likelihood estimation for an PR4-ML method detection error. Further, when a detected determination error matches an actual reproduction data string, a data correction circuit corrects the reproduction data string.

Abstract: A signal processing delay circuit is fabricated as a semiconductor integration circuit to cope with increase in the data transfer speed and data recording and reproducing density on a recording medium. In the delay circuit, the amount of delay of a reference delay circuit of a delay PLL is controlled to take a fixed value independent of deviation in quality of the semiconductor circuit, change in power, and alteration in temperature. A control signal supervising the delay amount of the reference delay circuit is employed to control amounts of delay of input signals supplied to a window adjustment delay circuit of a window adjustment circuit and a T/2 generation delay circuit generating a synchronizing signal. Each of these delay circuits includes an analog variable delay circuit having the same configuration. The window adjustment delay circuit is supervised by a signal obtained by weighting the control signal by a D/A converter.

Abstract: A voltage-controlled filter circuit has a cutoff frequency directly proportional to a ratio of two current values. The filter circuit comprises a variable conductance circuit having two bipolar junction input transistors supplied with an input voltage signal at the bases thereof and a first variable current source at each emitter thereof. The collectors supply the bases of a pair of differential transistors. A second variable current supply is coupled to common emitters of the pair of differential transistors. Externally supplied control signals set the two current values of the variable current sources. The filter circuit may be manufactured as a semiconductor integrated circuit device for signal processing for use in processing a recorded signal read from a recording medium. The recorded signal is supplied to a semiconductor integrated circuit for signal processing to remove unwanted signal and noise components.

Abstract: An active filter control apparatus for controlling or tuning an active filter having a variable cut-off frequency. The active filter control apparatus includes a control circuit for controlling or tuning the cut-off frequency of the active filter and a characteristic correction generator for generating a correction signal to correct a group delay characteristic of the active filter in accordance with a set cut-off frequency. The characteristic correction includes a correction signal generator for generating the correction signal in accordance with a set correction amount. The cut-off frequency controller controls tunes the characteristic of the active filter in accordance with the correction signal. Preferably, the apparatus is formed of a one-chip LSI integrated on one chip. The control apparatus can be utilized to control the speed in a recording/reproducing apparatus such as a optical disk drive or a magnetic tape drive apparatus.

Abstract: A data transfer system including an exchange, wherein the exchange transfers data by sharing a plurality of channels by a time division multiplex mode. In this case, the exchange transfers the data by variably allocating respective time slots to be occupied by the respective channels. That is, it is possible to allot any line speed to any channel and therefore possible to mix signals with different data transfer speeds in the frames. This results in an exchange network with a high degree of freedom of transfer for the subscriber terminal equipment.

Abstract: The semiconductor integrated circuit device formed on one semiconductor substrate employs a plurality of first and second circuit blocks constituting functions of the same kind. The first and second circuit blocks, however, are implemented with respectively different types of circuits. The type of circuit employed in the respective first and second circuit blocks is necessarily consistent with the particular operation speed requirements thereof, such as, in connection with high-speed and low-speed circuit requirements for writing into the memory of a display system.

Abstract: A packet data and a header added to a head of the packet data for specifying a transfer condition of the packet data are divided together to data blocks (DBs) each having a designated data length, consisting of an initial DB including the header and an initial part of the packet data, intermediate DBs each including an intermediate part of the packet data and a last DB including a last part of the packet data, so as to be transferred to a data transfer destination in a data processor of a switching system in accordance with write commands for the initial, intermediate and last DBs respectively, and a read command for asking whether the DBs are correctly transferred is sent to the data transfer destination once, after the DBs are transferred. When the DBs are transferred, the packet data is restored at the data transfer destination only by synthesizing the transferred DBs and removing the header.

Abstract: An electric contact with a base metal used as a switch wherein the non-welded peripheral portion of the contact is prevented from bow-like bending and from peeling off. The electric contact with a base metal having a contact promoting shape is formed by die forging of a contact material joined to the base metal by resistance welding. The composite contact material is prepared by coating the core material of Ag-oxide contact material with non-oxide contact material. The side of the material in contact with the base metal is of non-oxide contact material. The contact material may be pressed to fill a groove preformed in the base metal, welded to protrusions preformed in the base metal, welded to the bottom of a cut preformed in the base metal, or welded to bottoms of recesses preformed in the base metal.

Abstract: In the composition of a Ag alloy type material used for production of flutes, a specified amount of at least one of Ni, Fe, Co and Cr or at least one of Mn, Ti, Zi and Si is added to suppress softening and crystal grain size coarsening caused by annealing in production. Thus, flutes which generate brilliant sounds in mid to high notes can be obtained by using the above material.