Patents by Inventor Takashi Nihonmatsu

Takashi Nihonmatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7332437
    Abstract: There is provided a method for processing a semiconductor wafer subjected to a chamfering process, a lapping process, an etching process, and a mirror-polishing process, wherein acid etching is performed after alkaline etching as the etching process, and the acid etching is performed with an acid etchant composed of hydrofluoric acid, nitric acid, phosphoric acid, and water, a method for processing a semiconductor wafer subjected to a chamfering process, a surface grinding process, an etching process, and a mirror-polishing process, wherein the etching process is performed as described above, and a method for processing a semiconductor wafer subjected to a flattening process, an etching process, and a mirror-polishing process, wherein the etching process is performed as described above, a back surface polishing process is performed after the acid etching as the mirror-polishing process, and then a front surface polishing process is performed.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: February 19, 2008
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Takashi Nihonmatsu, Masahiko Yoshida, Yoshinori Sasaki, Masahito Saitoh, Toshiaki Takaku, Tadahiro Kato
  • Patent number: 6764392
    Abstract: A polishing method and polishing apparatus capable of improving the flatness of a wafer are provided. When a wafer is adhered to a wafer holding plate for polishing a surface to be polished of the wafer by pressing and rubbing the surface to be polished against a polishing pad on a polishing turn table, the wafer is held by vacuum-chucking the surface to be polished of the wafer such that a surface to be adhered of the wafer forms a convex surface in a vicinity including an arbitrary point in the surface to be adhered within a region surrounding a center of the surface to be adhered of the wafer, and the region being at least not less than 50% of an entire adhesion area; and the wafer is adhered to the wafer holding plate from a central portion of the surface to be adhered of the wafer.
    Type: Grant
    Filed: August 16, 2001
    Date of Patent: July 20, 2004
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Takashi Nihonmatsu, Takahiro Kida, Tadao Tanaka
  • Publication number: 20040072437
    Abstract: The present invention relates to a method for producing a silicon wafer, wherein the method comprises at least a lapping process by use of loose abrasive grains and an etching process by use of an alkaline etching solution, lapping is performed in the lapping process by use of abrasive grains having a maximum grain diameter of 21 &mgr;m or less and an average grain diameter of 8.5 &mgr;m or less serving as the loose abrasive grains, and after that, etching is performed in the etching process by use of an alkaline solution having a concentration of an alkaline component of 50% by weight or more serving as the alkaline etching solution, and relates to a silicon wafer produced by the production method. Thus, there can be provided a method for producing a silicon wafer which can prevent degradation of surface roughness of the wafer and flatness of the whole wafer, and a silicon wafer produced by the method.
    Type: Application
    Filed: July 31, 2003
    Publication date: April 15, 2004
    Inventors: Naoto Iizuka, Takashi Nihonmatsu, Masahiko Yoshida, Seiichi Miyazaki
  • Publication number: 20030171075
    Abstract: There is provided a method for processing a semiconductor wafer subjected to a chamfering process, a lapping process, an etching process, and a mirror-polishing process, wherein acid etching is performed after alkaline etching as the etching process, and the acid etching is performed with an acid etchant composed of hydrofluoric acid, nitric acid, phosphoric acid, and water, a method for processing a semiconductor wafer subjected to a chamfering process, a surface grinding process, an etching process, and a mirror-polishing process, wherein the etching process is performed as described above, and a method for processing a semiconductor wafer subjected to a flattening process, an etching process, and a mirror-polishing process, wherein the etching process is performed as described above, a back surface polishing process is performed after the acid etching as the mirror-polishing process, and then a front surface polishing process is performed.
    Type: Application
    Filed: December 27, 2002
    Publication date: September 11, 2003
    Inventors: Takashi Nihonmatsu, Masahiko Yoshida, Yoshinori Sasaki, Masahito Saitoh, Toshiaki Takaku, Tadahiro Kato
  • Publication number: 20020160693
    Abstract: A polishing method and polishing apparatus capable of improving the flatness of a wafer are provided. When a wafer is adhered to a wafer holding plate for polishing a surface to be polished of the wafer by pressing and rubbing the surface to be polished against a polishing pad on a polishing turn table, the wafer is held by vacuum-chucking the surface to be polished of the wafer such that a surface to be adhered of the wafer forms a convex surface in a vicinity including an arbitrary point in the surface to be adhered within a region surrounding a center of the surface to be adhered of the wafer, and the region being at least not less than 50% of an entire adhesion area; and the wafer is adhered to the wafer holding plate from a central portion of the surface to be adhered of the wafer.
    Type: Application
    Filed: August 16, 2001
    Publication date: October 31, 2002
    Inventors: Takashi Nihonmatsu, Takahiro Kida, Tadao Tanaka
  • Patent number: 6432837
    Abstract: A method of processing a semiconductor wafer sliced from a monocrystalline ingot comprises at least the steps of chamfering, lapping, etching, mirror-polishing, and cleaning. In the etching step, alkali etching is first performed and then acid etching, preferably reaction-controlled acid etching, is performed. The etching amount of the alkali etching is greater than the etching amount of the acid etching. Alternatively, in the etching step, reaction-controlled acid etching is first performed and then diffusion-controlled acid etching is performed. The etching amount of the reaction-controlled acid etching is greater than the etching amount of the diffusion-controlled acid etching.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: August 13, 2002
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Takashi Nihonmatsu, Seiichi Miyazaki, Masahiko Yoshida, Hideo Kudo, Tadahiro Kato
  • Patent number: 6346485
    Abstract: A method of processing a semiconductor wafer sliced from a monocrystalline ingot comprises at least the steps of chamfering, lapping, etching, mirror-polishing, and cleaning. In the etching step, alkali etching is first performed and then acid etching, preferably reaction-controlled acid etching, is performed. The etching amount of the alkali etching is greater than the etching amount of the acid etching. Alternatively, in the etching step, reaction-controlled acid etching is first performed and then diffusion-controlled acid etching is performed. The etching amount of the reaction-controlled acid etching is greater than the etching amount of the diffusion-controlled acid etching.
    Type: Grant
    Filed: August 7, 2000
    Date of Patent: February 12, 2002
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Takashi Nihonmatsu, Seiichi Miyazaki, Masahiko Yoshida, Hideo Kudo, Tadahiro Kato
  • Publication number: 20010008807
    Abstract: A method of processing a semiconductor wafer sliced from a monocrystalline ingot comprises at least the steps of chamfering, lapping, etching, mirror-polishing, and cleaning. In the etching step, alkali etching is first performed and then acid etching, preferably reaction-controlled acid etching, is performed. The etching amount of the alkali etching is greater than the etching amount of the acid etching. Alternatively, in the etching step, reaction-controlled acid etching is first performed and then diffusion-controlled acid etching is performed. The etching amount of the reaction-controlled acid etching is greater than the etching amount of the diffusion-controlled acid etching.
    Type: Application
    Filed: February 7, 2001
    Publication date: July 19, 2001
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Takashi Nihonmatsu, Seiichi Miyazaki, Masahiko Yoshida, Hideo Kudo
  • Patent number: 6239039
    Abstract: A method of processing a semiconductor wafer sliced from a monocrystalline ingot comprises at least the steps of chamfering, lapping, etching, mirror-polishing, and cleaning. In the etching step, alkali etching is first performed and then acid etching, preferably reaction-controlled acid etching, is performed. The etching amount of the alkali etching is greater than the etching amount of the acid etching. Alternatively, in the etching step, reaction-controlled acid etching is first performed and then diffusion-controlled acid etching is performed. The etching amount of the reaction-controlled acid etching is greater than the etching amount of the diffusion-controlled acid etching.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: May 29, 2001
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Takashi Nihonmatsu, Seiichi Miyazaki, Masahiko Yoshida, Hideo Kudo, Tadahiro Kato
  • Patent number: 6080641
    Abstract: There is disclosed a method of manufacturing semiconductor wafers, in which a lapping process is performed prior to a chamfering process. This makes it possible to manufacture semiconductor wafers while maintaining the smoothness and dimensional accuracy of a chamfered surface of each wafer obtained by the chamfering process.
    Type: Grant
    Filed: May 19, 1997
    Date of Patent: June 27, 2000
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Takashi Nihonmatsu, Makoto Osuga
  • Patent number: 4168437
    Abstract: The method for efficiently measuring the thickness or surface flatness of, for example, a high-purity silicon semiconductor wafer uses a table to mount the wafer and a plurality of optoelectric sensors, each sensor being movable in the direction perpendicular to the table. The sensors are designed to project light beams to the measuring points set forth on the wafer surface. The light beam reflected from each measuring point is detected by a detector there. To the detector is connected a photoelectric transducer which generates electric signals corresponding to the distance of each measuring point from a reference surface, so that thickness variations can be found. In a preferred embodiment, the sensors are arranged in linear rows at regular intervals and the wafer surface is scanned with the light beams so that all measuring points distributed lattice-wise at regular intervals on the wafer surface are covered.
    Type: Grant
    Filed: September 13, 1977
    Date of Patent: September 18, 1979
    Assignees: Nagano Electronics Industrial Co., Ltd., Nidek Co., Ltd.
    Inventor: Takashi Nihonmatsu