Abstract: A semiconductor device including a substrate, a P-MOS single crystal TFT formed on the substrate, and an N-MOS single crystal TFT formed on the P-MOS single crystal TFT. The source region of the P-MOS single crystal TFT and the source region of the N-MOS single crystal TFT may be connected to each other. The P-MOS single crystal TFT and the N-MOS single crystal TFT may share a common gate. Also, the P-MOS single crystal TFT may include a single crystal silicon layer with a crystal plane of (100) and a crystal direction of <100>. The N-MOS single crystal TFT may include a single crystal silicon layer having the same crystal direction as the single crystal silicon layer of the P-MOS single crystal TFT and having a tensile stress greater than the single crystal silicon layer of the P-MOS single crystal TFT.

Abstract: Stacked transistors and electronic devices including the stacked transistors. An electronic device includes a substrate, a first transistor on the substrate and including a first active layer, a first gate, and a first gate insulating layer between the first active layer and the first gate, a first metal line spaced apart from the first gate on the substrate, a first insulating layer covering the first transistor and the first metal line, and a second transistor on the first insulating layer between the first transistor and the first metal line, and including a second active layer, a second gate, and a second gate insulating layer between the second active layer and the second gate.

Abstract: Provided are a poly crystalline silicon semiconductor device and a method of fabricating the same. Portions of a silicon layer except for gates are removed to reduce a parasitic capacitance caused from the silicon layer existing on gate bus lines. The silicon layer exists under the gates only, thus the parasitic capacitance is reduced and the deterioration and the delay of signals are prevented. Accordingly, the poly crystalline silicon semiconductor device, such as a thin film transistor, has excellent electric characteristics.

Abstract: A transistor includes; at least two polycrystalline silicon layers disposed substantially parallel to each other, each polycrystalline silicon layer including a channel region and at least two high conductivity regions disposed at opposing sides of the channel region; a gate which corresponds to the channel region of the two polycrystalline silicon layers and which crosses the two polycrystalline silicon layers, and a gate insulating layer interposed between the gate and the two polycrystalline silicon layers, wherein low conductivity regions are disposed adjacent to one edge of the gate and are formed between the channel region and one high conductivity region of each polycrystalline silicon layer.

Abstract: A method for producing an optical article. A first layer that is light-transmissive is formed on an optical substrate directly or with an additional layer in between. A silicide material, light-transmissive thin film is formed on the surface of the first layer.

Abstract: An organic electroluminescent display (“OELD”) includes an organic light-emitting diode (“OLED”), a circuit region, and an interlayer dielectric (“ILD”) layer. The OLED is disposed in each of a plurality of pixels arranged on a substrate. The circuit region includes two or more thin film transistors (“TFTs”) and a storage capacitor. The ILD layer has two or more insulating layers and includes a first region disposed between both electrodes of the storage capacitor and a second region covering the TFTs. At least one of the insulating layers has a window exposing the insulating layer directly beneath the at least one insulating layer so that that the ILD layer is thinner in the first region than in the second region. Accordingly, it is possible to reduce an occupation area of the storage capacitor while maintaining the necessary capacitance of the storage capacitor and expanding the area of the luminescent region.

Abstract: A method of manufacturing a polycrystalline Si film and a method of manufacturing a stacked transistor are provided. The method of manufacturing the polycrystalline Si film includes preparing an insulating substrate on which is formed a transistor that includes a poly-Si active layer, a gate insulating layer, and a gate, sequentially formed, forming an interconnection metal line separated from the gate, forming an insulating layer that covers the transistor and the interconnection metal line, forming an amorphous silicon layer on the insulating layer; and annealing the amorphous silicon layer.

Abstract: A silicon nanowire substrate having a structure in which a silicon nanowire film having a fine line-width is formed on a substrate, a method of manufacturing the same, and a method of manufacturing a thin film transistor using the same. The method of manufacturing the silicon nanowire substrate includes preparing a substrate, forming an insulating film on the substrate, forming a silicon film on the insulating film, patterning the insulating film and the silicon film into a strip shape, reducing the line-width of the insulating film by undercut etching at least one lateral side of the insulating film, and forming a self-aligned silicon nanowire film on an upper surface of the insulating film by melting and crystallizing the silicon film.

Abstract: A semiconductor device includes a transistor. The transistor includes a substrate having an inclined surface, a first upper surface extending from a lower portion of the inclined surface, and a second upper surface extending from an upper end of the inclined surface. A gate stack structure is formed on the inclined surface and includes a gate electrode. A first impurity region formed on one of the first and second upper surfaces contacts the gate stack structure. A second impurity region formed on the second upper surface contacts the gate stack structure. A channel between the first and second impurity regions is formed along the inclined surface in a crystalline direction.

Abstract: An organic electroluminescent display (“OELD”) includes an organic light-emitting diode (“OLED”), a circuit region, and an interlayer dielectric (“ILD”) layer. The OLED is disposed in each of a plurality of pixels arranged on a substrate. The circuit region includes two or more thin film transistors (“TFTs”) and a storage capacitor. The ILD layer has two or more insulating layers and includes a first region disposed between both electrodes of the storage capacitor and a second region covering the TFTs. At least one of the insulating layers has a window exposing the insulating layer directly beneath the at least one insulating layer so that that the ILD layer is thinner in the first region than in the second region. Accordingly, it is possible to reduce an occupation area of the storage capacitor while maintaining the necessary capacitance of the storage capacitor and expanding the area of the luminescent region.

Abstract: An optical article includes an anti-reflection layer on a substrate, wherein the anti-reflection layer is formed of nine layers obtained by alternately stacking low refractive index layers and high refractive index layers, the layer closest to the substrate among the high and low refractive index layers that form the anti-reflection layer is called a first layer and the numbers of the following layers are incremented by one so that the odd-numbered layers are low refractive index layers and the even-numbered layers are high refractive index layers, and at least one of the following equations is satisfied: 0.8?0??1?1.2?0??(1) 0.8?0??3?1.2?0??(2) where ?0 represents a design primary wavelength greater than or equal to 480 nm but smaller than or equal to 550 nm, and ?k represents the optical thickness of the corresponding one of the high and low refractive index layers (k represents the layer number).

Abstract: A multilayer antireflection layer includes a high refractive index layer and a low refractive index layer that are laminated alternately, the high reflective index layer having a grain boundary, and particles forming the grain boundary having an average particle diameter of 30 nm or less.

Abstract: A transistor includes; at least two polycrystalline silicon layers disposed substantially parallel to each other, each polycrystalline silicon layer including a channel region and at least two high conductivity regions disposed at opposing sides of the channel region; a gate which corresponds to the channel region of the two polycrystalline silicon layers and which crosses the two polycrystalline silicon layers, and a gate insulating layer interposed between the gate and the two polycrystalline silicon layers, wherein low conductivity regions are disposed adjacent to one edge of the gate and are formed between the channel region and one high conductivity region of each polycrystalline silicon layer.

Abstract: A fabricating method for a semiconductor device includes forming a heat spreading material on rear surface of the semiconductor wafer. The semiconductor wafer has a plurality of device areas and scribe lines which are arranged between the device areas. After the heat spreading material is formed on rear surface of the semiconductor wafer, the semiconductor wafer is separated at the scribe lines.

Abstract: Provided is a strained SOI structure and a method of manufacturing the strained SOI structure. The strained SOI structure includes an insulating substrate, a SiO2 layer formed on the insulating substrate, and a strained silicon layer formed on the SiO2 layer.

Abstract: A discharge lamp configured to suppress temperature increases in the electrode on the opening part side of a reflective mirror is described. The discharge lamp includes an F electrode and an R electrode having shapes before forming the melt electrodes that satisfy at least one of the following conditions (a) to (c): (a) The diameter of the core wire of the F electrode is d1f, and the diameter of the core wire of the R electrode is d1r, then d1f>1.2×d1r; (b) The wire diameter of the coil of said F electrode is d2f, and the wire diameter of the coil of the R electrode is d2r, then d2f>1.2×d2r; (c) the number of windings of the coil of the F electrode is nf, and the number of windings of the coil of the R electrode is nr, then nf>1.2×nr.