Patents by Inventor Takashi Ohya

Takashi Ohya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7049437
    Abstract: The present invention provides a process of a compound of the formula (I): wherein R is heteroaryl or the like, ring A is a heteroalicyclic group or the like comprising reacting a compound of the formula (II): wherein Hal is halogen and the other symbols are the same as the above, in the presence of a sulfinic acid salt and further in the presence of an acid or a salt with an organic base, and a novel crystal form of 2-(3-isoxazolyl)-3,6,7,9-tetrahydroimidazo[4,5-d]pyrano[4,3-b]pyridine phosphate monohydrate.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: May 23, 2006
    Assignee: Shionogi & Co., Ltd.
    Inventors: Fumihiko Matsubara, Takashi Ohya, Masaaki Uenaka
  • Publication number: 20030088102
    Abstract: The present invention provides a process of a compound of the formula (I): 1
    Type: Application
    Filed: September 25, 2002
    Publication date: May 8, 2003
    Inventors: Fumihiko Matsubara, Takashi Ohya, Masaaki Uenaka
  • Patent number: 6479671
    Abstract: A process for producing a compound of the formula (II): (wherein R1, R2, R3 and R4 are each independently hydrogen, alkyl, alkoxy or the like, R5 is alkyl or alkoxyalkyl, A is O or S, Ar is aryl or the like, * represents the position of an asymmetric carbon atom and that the compound is the (R) or (S) isomer and Q is an optical resolution reagent) comprising isolating the compound as crystals from a solution or suspension containing the compound of the formula (II) (wherein * represents that the compound is the (R) or (S) isomer or a mixture thereof and the other symbols are the same as the above).
    Type: Grant
    Filed: August 15, 2000
    Date of Patent: November 12, 2002
    Assignee: Shionogi & Co., Ltd.
    Inventors: Toshiro Konoike, Tadahiko Yorifuji, Shoji Shinomoto, Yutaka Ide, Takashi Ohya, Ken-ichi Matsumura
  • Patent number: 4894564
    Abstract: A programmable logic array comprises an OR circuit (67) and an AND circuit (68). A voltage lower than a power-supply voltage is applied to product term lines (57-60) from a power supply portion (69) in response to conduction of p channel transistors (31-34) by a clock signal to be precharged, and a voltage lower than the power-supply voltage is applied to output lines (54, 55) from a power supply portion (70) in response to conduction of p channel transistors (39, 40) by the clock signal. Therefore, applied voltages of the product term lines and the output lines are lowered, so that responsibility of circuit is improved, whereby a programmable logic array with a high speed operation is obtained.
    Type: Grant
    Filed: October 6, 1988
    Date of Patent: January 16, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuhiro Sakashita, Takashi Ohya, Takeshi Hashizume