Abstract: A semiconductor device includes: a semiconductor substrate; a plurality of first pad electrodes provided above the semiconductor substrate; a plurality of first wires electrically connected to the plurality of first pad electrodes respectively; a first electrode commonly connected to the plurality of first wires; a second pad electrode provided above the semiconductor substrate; and a first resistance portion and a first protective element that are connected in series between the first electrode and the second pad electrode.

Abstract: A semiconductor device includes: a semiconductor substrate; a plurality of first pad electrodes provided above the semiconductor substrate; a plurality of first wires electrically connected to the plurality of first pad electrodes respectively; a first electrode commonly connected to the plurality of first wires; a second pad electrode provided above the semiconductor substrate; and a first resistance portion and a first protective element that are connected in series between the first electrode and the second pad electrode.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a first electrode, a first insulating layer, and a second electrode. The first semiconductor region includes a first region and a second region. The second semiconductor region is provided on the first semiconductor region in the first region. The third semiconductor region is provided on the first semiconductor region in the second region. The first electrode is provided on the third semiconductor region. The first electrode is electrically connected to the third semiconductor region. The first insulating layer is provided on the first electrode. The second electrode is provided on the second semiconductor region. A portion of the second electrode is positioned on the first insulating layer.

Abstract: A semiconductor device according to an embodiment includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a first electrode, a gate electrode, a third insulating layer, a second electrode, a third electrode, and a fourth electrode. The third insulating layer is provided between the gate electrode and the first semiconductor region, between the gate electrode and the second semiconductor region, and between the gate electrode and the third semiconductor region. The second electrode is electrically connected to the third semiconductor region. The third electrode is spaced from the second electrode. The third electrode is electrically connected to the gate electrode. The fourth electrode is electrically connected to the first electrode. The fourth electrode is spaced from the second electrode and the third electrode.

Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, an element region, a terminal region, and a second electrode. The element region includes a second semiconductor region of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a gate electrode, and a first electrode. The terminal region includes a fifth semiconductor region of the second conductivity type, and a sixth semiconductor region of the second conductivity type. The terminal region surrounds the element region. The fifth semiconductor region is provided within the first semiconductor region. A plurality of the fifth semiconductor regions are provided along a second direction. The sixth semiconductor region is provided between the first semiconductor region and the fifth semiconductor region. A dopant of the sixth semiconductor region is higher than a dopant concentration of the fifth semiconductor region.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type which is provided on the first semiconductor layer, a third semiconductor layer of the first conductivity type which is selectively provided on a surface of the second semiconductor layer, an insulating film which is provided to cover an inner wall of a trench running into the first semiconductor layer from an upper face of the third semiconductor layer, a field plate electrode which is provided in a lower portion of the trench, a gate electrode which is provided on the field plate electrode via the insulating film, and a fourth semiconductor layer of the second conductivity type which is provided at least in a region direct below the trench, and comes into contact with the insulating film.